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    Method of fabricating bipolar transistor having high speed and MOS transistor having small size
    1.
    发明授权
    Method of fabricating bipolar transistor having high speed and MOS transistor having small size 失效
    制造具有高速度的双极晶体管的方法和具有小尺寸的MOS晶体管

    公开(公告)号：US5506156A

    公开(公告)日：1996-04-09

    申请号：US279087

    申请日：1994-07-22

    申请人： Atsuo Watanabe ,  Kazushige Sato ,  Takahiro Nagano ,  Shoji Shukuri ,  Takashi Nishida

    发明人： Atsuo Watanabe ,  Kazushige Sato ,  Takahiro Nagano ,  Shoji Shukuri ,  Takashi Nishida

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/265

    CPC分类号： H01L21/8249 ,  Y10S148/009

    摘要： A semiconductor device includes a plurality of semiconductor regions of a first conductive type and a plurality of semiconductor regions of a second conductive type. AMOS transistor having a channel of the second conductive type is formed in the semiconductor regions of the first conductive type, and a bipolar transistor and a MOS transistor having a channel of the first conductive type are formed in the semiconductor regions of the second conductive type. Each of the semiconductor regions of the first conductive type is made up of a semiconductor layer where the impurity concentration decreases with the depth from the surface thereof, a first buried layer of the first conductive type which is formed in a semiconductor substrate and where the impurity concentration distribution in the direction of thickness has a single peak value, and a second buried layer of the first conductive type which is formed between the semiconductor layer and the first buried layer and where the impurity concentration distribution in the direction of thickness has a single peak value. The first and second buried layers are formed by the ion implantation method, after an epitaxial growth process and a field oxidation process have been completed.

    摘要翻译： 半导体器件包括多个第一导电类型的半导体区域和第二导电类型的多个半导体区域。 具有第二导电类型的沟道的AMOS晶体管形成在第一导电类型的半导体区域中，并且在第二导电类型的半导体区域中形成具有第一导电类型的沟道的双极晶体管和MOS晶体管。 第一导电类型的半导体区域由半导体层构成，其中杂质浓度随着其表面的深度而减小，第一导电类型的第一掩埋层形成在半导体衬底中，并且杂质 在厚度方向上的浓度分布具有单个峰值，并且形成在半导体层和第一掩埋层之间的第一导电类型的第二掩埋层，并且其中厚度方向上的杂质浓度分布具有单峰 值。 在外延生长处理和场氧化处理完成之后，通过离子注入法形成第一和第二掩埋层。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US5055904A

    公开(公告)日：1991-10-08

    申请号：US495762

    申请日：1990-03-19

    申请人： Masataka Minami ,  Kazushige Sato ,  Atsuo Watanabe ,  Shoji Shukuri ,  Takashi Nishida ,  Takahiro Nagano

    发明人： Masataka Minami ,  Kazushige Sato ,  Atsuo Watanabe ,  Shoji Shukuri ,  Takashi Nishida ,  Takahiro Nagano

    IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L27/11

    CPC分类号： H01L27/0623 ,  H01L27/1112 ,  Y10S257/903

    摘要： A semicondcutor device and a manufacturing method thereof are disclosed in which higher integration can be achieved without increasing the total manufacturing steps. The semiconductor device includes at least two MOS transistors having the same channel types, the gate electrodes of which are constructed of polycrystal silicon layers which contain an impurity, and a bipolar transistor, the base electrode of which is constructed of a polycrystal silicon layer which contains and impurity. In particular, the respective gate electrodes of the two MOS transistors contain impurities of different conductivity types from one another.

    摘要翻译： 公开了一种半切割器件及其制造方法，其中可以在不增加总制造步骤的情况下实现更高的集成度。 半导体器件包括至少两个具有相同沟道类型的MOS晶体管，其栅电极由含有杂质的多晶硅层构成;以及双极晶体管，其基极由多晶硅层构成，该多晶硅层含有 和杂质。 特别地，两个MOS晶体管的各个栅电极彼此具有不同导电类型的杂质。

    Semiconductor device and manufacturing method thereof
    3.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US07776495B2

    公开(公告)日：2010-08-17

    申请号：US11725507

    申请日：2007-03-20

    申请人： Masahito Hiroshima ,  Takashi Nishida

    发明人： Masahito Hiroshima ,  Takashi Nishida

    IPC分类号： G03F7/00

    CPC分类号： H01L28/91 ,  G03F1/00 ,  H01L27/10808 ,  H01L27/10852

    摘要： A semiconductor device and a manufacturing method thereof in which the peripheral length of an aperture and the mechanical strength of cylinders in a cell can be increased without changing the occupation rate of patterns in the cell. By forming a slit in the middle of each mask pattern so as not to expose parts of wafer, the aperture of the wafer becomes nearly cocoon-shaped with a constriction in the middle. Thereby, the peripheral length of the aperture can be increased without changing the occupation rate of the mask patterns in a cell. Further, the shape of the bottom of the aperture also becomes nearly cocoon-shaped with a constriction in the middle, and therefore it is possible to increase the mechanical strength of cylinders.

    摘要翻译： 一种半导体器件及其制造方法，其中可以增加孔的圆周长度和单元中气缸的机械强度，而不改变单元中图案的占用率。 通过在每个掩模图案的中间形成狭缝以不暴露晶片的一部分，晶片的孔径在中间收缩而变为几乎茧形。 因此，可以增加孔径的周长，而不改变单元中的掩模图案的占有率。 此外，孔的底部的形状也变得几乎茧形，中间有收缩，因此可以提高气缸的机械强度。

    Semiconductor device and manufacturing method thereof
    4.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US07208788B2

    公开(公告)日：2007-04-24

    申请号：US10995134

    申请日：2004-11-24

    申请人： Masahito Hiroshima ,  Takashi Nishida

    发明人： Masahito Hiroshima ,  Takashi Nishida

    IPC分类号： H01L29/73

    CPC分类号： H01L28/91 ,  G03F1/00 ,  H01L27/10808 ,  H01L27/10852

    摘要： A semiconductor device and a manufacturing method thereof in which the peripheral length of an aperture and the mechanical strength of cylinders in a cell can be increased without changing the occupation rate of patterns in the cell. By forming a slit in the middle of each mask pattern so as not to expose parts of wafer, the aperture of the wafer becomes nearly cocoon-shaped with a constriction in the middle. Thereby, the peripheral length of the aperture can be increased without changing the occupation rate of the mask patterns in a cell. Further, the shape of the bottom of the aperture also becomes nearly cocoon-shaped with a constriction in the middle, and therefore it is possible to increase the mechanical strength of cylinders.

    摘要翻译： 一种半导体器件及其制造方法，其中可以增加孔的圆周长度和单元中气缸的机械强度，而不改变单元中图案的占用率。 通过在每个掩模图案的中间形成狭缝以不暴露晶片的一部分，晶片的孔径在中间收缩而变为几乎茧形。 因此，可以增加孔径的周长，而不改变单元中的掩模图案的占有率。 此外，孔的底部的形状也变得几乎茧形，中间有收缩，因此可以提高气缸的机械强度。

    Semiconductor memory device having flip-flop circuits
    5.
    发明授权
    Semiconductor memory device having flip-flop circuits 失效
    具有触发电路的半导体存储器件

    公开(公告)号：US5132771A

    公开(公告)日：1992-07-21

    申请号：US503928

    申请日：1990-04-04

    申请人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    发明人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    IPC分类号： G11C11/412 ,  H01L27/11

    CPC分类号： G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

    摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

    摘要翻译： 提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。 半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。 每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。 两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极 另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。 此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以 彼此平行。