摘要:
A semiconductor device has a well region formed in the surface of a substrate, and has functional portions such as MOSFET and bipolar transistor formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.
摘要翻译:半导体器件具有在衬底的表面中形成的阱区,并且具有形成在阱区中的诸如MOSFET和双极晶体管的功能部分。 阱区域的载流子浓度分布呈深谷方向的谷状,其最小点浓度小于5×10 15 cm -3,位于距离其表面1.6m以内的位置 底物。 优选地,最小点应该具有大于5×10 14 cm -3但小于5×10 15 cm -3的浓度,更优选大于1×10 15 cm -3但小于5×10 15 cm -3的浓度。
摘要:
A semiconductor device has a well region formed in the surface of a substrate, and has semiconductor elements such as MOSFETs and bipolar transistors formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.
摘要翻译:半导体器件具有在衬底的表面中形成的阱区,并且在阱区中形成有诸如MOSFET和双极晶体管的半导体元件。 阱区域的载流子浓度分布呈深谷方向的谷状,其最小点浓度小于5×10 15 cm -3,位于距离其表面1.6m以内的位置 底物。 优选地,最小点应该具有大于5×10 14 cm -3但小于5×10 15 cm -3的浓度,更优选大于1×10 15 cm -3但小于5×10 15 cm -3的浓度。
摘要:
The present invention relates to a semiconductor device comprising a semiconductor substrate of a first conductivity type or an insulator, a source comprising an impurity layer of a second conductivity type disposed on said semiconductor substrate or said insulator, a drain comprising an impurity layer of the second conductivity type disposed on said semiconductor substrate or said insulator, an impurity layer of the first conductivity type formed between said source and said drain, a gate formed on said impurity layer of the first conductivity type via an insulation film, and an impurity layer of the second conductivity type having an impurity concentration lower than that of said source and said drain, said impurity layer of the second conductivity type being disposed between said source, said drain and said impurity layer of the first conductivity type, and said semiconductor substrate of the first conductivity type or said insulator.
摘要:
Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要:
Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要:
Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要:
Herein disclosed is a semiconductor integrated circuit device comprising a SRAM which is composed of a memory cell having its high resistance load element and power source voltage line connected with the information storage node of a flip-flop circuit through a conductive layer. At the same fabrication step as that of forming the plate electrode layer of a capacity element over the conductive layer formed on the portion of the information storage node through a dielectric film, an electric field shielding film for shielding the field effect of a data line is formed over the high resistance load element through an inter-layer insulation film.
摘要:
An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.
摘要:
A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
摘要:
A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.