公开(公告)号：US20090086522A1

公开(公告)日：2009-04-02

申请号：US12239900

申请日：2008-09-29

申请人： Atsushi HIRAISHI ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

发明人： Atsushi HIRAISHI ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

IPC分类号： G11C5/06 ,  H05K1/18 ,  H05K7/00

CPC分类号： G11C5/063 ,  G11C5/04 ,  G11C8/14 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/10159 ,  Y02P70/611

摘要： An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.

摘要翻译： 具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。 数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。 从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。 从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。