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公开(公告)号：US08922029B2
公开(公告)日：2014-12-30
申请号：US13363396
申请日：2012-02-01
申请人： Atsushi Hiraishi , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
发明人： Atsushi Hiraishi , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
CPC分类号： G11C5/063 , G11C5/04 , G11C8/14 , H05K1/181 , H05K2201/09254 , H05K2201/09263 , H05K2201/10159 , Y02P70/611
摘要： An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.
摘要翻译： 具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。 数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。 从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。 从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。
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2.发明授权公开(公告)号：US08134239B2
公开(公告)日：2012-03-13
申请号：US12239900
申请日：2008-09-29
申请人： Atsushi Hiraishi , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
发明人： Atsushi Hiraishi , Toshio Sugano , Masahiro Yamaguchi , Yoji Nishio , Tsutomu Hara , Koichiro Aoki
CPC分类号： G11C5/063 , G11C5/04 , G11C8/14 , H05K1/181 , H05K2201/09254 , H05K2201/09263 , H05K2201/10159 , Y02P70/611
摘要： An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.
摘要翻译： 具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。 数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。 从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。 从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。
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公开(公告)号：US07667317B2
公开(公告)日：2010-02-23
申请号：US11802888
申请日：2007-05-25
申请人： Fumiyuki Osanai , Atsushi Hiraishi , Toshio Sugano , Tsuyoshi Tomoyama , Satoshi Isa , Masahiro Yamaguchi , Masanori Shibamoto
发明人： Fumiyuki Osanai , Atsushi Hiraishi , Toshio Sugano , Tsuyoshi Tomoyama , Satoshi Isa , Masahiro Yamaguchi , Masanori Shibamoto
IPC分类号： H01L23/055
CPC分类号： H01L23/50 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/19041 , H01L2924/3011 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.
摘要翻译： 半导体封装包括具有两个表面并且包括第一和第二电路径的衬底。 在其中一个表面上安装了半导体芯片。 半导体芯片包括多个焊盘，其包括要供应电源的第一焊盘和要接地的第二焊盘。 在另一个表面上，安装至少一个旁路电容器。 旁路电容器包括分别通过第一和第二电路连接到第一和第二焊盘的第一和第二端子。
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公开(公告)号：US20070273021A1
公开(公告)日：2007-11-29
申请号：US11802888
申请日：2007-05-25
申请人： Fumiyuki Osanai , Atsushi Hiraishi , Toshio Sugano , Tsuyoshi Tomoyama , Satoshi Isa , Masahiro Yamaguchi , Masanori Shibamoto
发明人： Fumiyuki Osanai , Atsushi Hiraishi , Toshio Sugano , Tsuyoshi Tomoyama , Satoshi Isa , Masahiro Yamaguchi , Masanori Shibamoto
IPC分类号： H01L23/12
CPC分类号： H01L23/50 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/19041 , H01L2924/3011 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.
摘要翻译： 半导体封装包括具有两个表面并且包括第一和第二电路径的衬底。 在其中一个表面上安装了半导体芯片。 半导体芯片包括多个焊盘，其包括要供应电源的第一焊盘和要接地的第二焊盘。 在另一个表面上，安装至少一个旁路电容器。 旁路电容器包括分别通过第一和第二电路连接到第一和第二焊盘的第一和第二端子。
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公开(公告)号：US08064236B2
公开(公告)日：2011-11-22
申请号：US12477501
申请日：2009-06-03
申请人： Yoji Nishio , Atsushi Hiraishi
发明人： Yoji Nishio , Atsushi Hiraishi
IPC分类号： G11C5/02
CPC分类号： G11C5/04 , G06F13/4072 , G06F13/4086 , H01L2224/06136 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73265 , H01L2924/15192 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： In a multi-rank memory module having a terminal resistance of a data input/output pad 13 and a terminal resistance control pad 14 that inputs a signal that controls on/off of the terminal resistance, a high-speed operation is enabled with the aid of an enclosed terminal resistance, even in cases where the number of ranks is greater than that of terminal resistance control terminals (ODT terminals) provided on the memory module. To this end, a terminal resistance control pad 14 of a memory chip 12, having a longer length of an interconnect between a data bus 19 on a module substrate 8 and a data input/output pad 13, is connected to a terminal resistance control interconnect 18 or 21 to control the on/off of the terminal resistance from the ODT terminal. A terminal resistance control pad on a memory chip 11, having a shorter length of an interconnect between the data bus 19 on the module substrate and the data input/output pad 13, is connected to a fixed potential 20 to turn on the terminal resistance.
摘要翻译： 在具有数据输入/输出焊盘13的终端电阻的多级存储器模块和输入控制端子电阻的接通/断开的信号的端子电阻控制焊盘14的情况下，可以借助于高速操作 即使在排列数大于设置在存储器模块上的端子电阻控制端子（ODT端子）的数量的情况下，也可以是封闭的端子电阻。 为此，在模块基板8上的数据总线19与数据输入/输出焊盘13之间具有较长互连长度的存储芯片12的端子电阻控制焊盘14连接到终端电阻控制互连 18或21以控制来自ODT端子的端子电阻的开/关。 在模块基板上的数据总线19与数据输入/输出焊盘13之间的互连的较短长度的存储芯片11上的端子电阻控制焊盘连接到固定电位20以接通端子电阻。
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公开(公告)号：US5854562A
公开(公告)日：1998-12-29
申请号：US842536
申请日：1997-04-15
申请人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
发明人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
IPC分类号： G11C11/419 , G11C7/06 , G11C11/409
CPC分类号： G11C7/065
摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being of 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
摘要翻译： 一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管 到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。 基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以减少输出响应的延迟时间。
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公开(公告)号：US20090303768A1
公开(公告)日：2009-12-10
申请号：US12477501
申请日：2009-06-03
申请人： Yoji NISHIO , Atsushi Hiraishi
发明人： Yoji NISHIO , Atsushi Hiraishi
CPC分类号： G11C5/04 , G06F13/4072 , G06F13/4086 , H01L2224/06136 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73265 , H01L2924/15192 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： In a multi-rank memory module having a terminal resistance of a data input/output pad 13 and a terminal resistance control pad 14 that inputs a signal that controls on/off of the terminal resistance, a high-speed operation is enabled with the aid of an enclosed terminal resistance, even in cases where the number of ranks is greater than that of terminal resistance control terminals (ODT terminals) provided on the memory module. To this end, a terminal resistance control pad 14 of a memory chip 12, having a longer length of an interconnect between a data bus 19 on a module substrate 8 and a data input/output pad 13, is connected to a terminal resistance control interconnect 18 or 21 to control the on/off of the terminal resistance from the ODT terminal. A terminal resistance control pad on a memory chip 11, having a shorter length of an interconnect between the data bus 19 on the module substrate and the data input/output pad 13, is connected to a fixed potential 20 to turn on the terminal resistance.
摘要翻译： 在具有数据输入/输出焊盘13的终端电阻的多级存储器模块和输入控制端子电阻的接通/断开的信号的端子电阻控制焊盘14的情况下，可以通过辅助来实现高速操作 即使在排列数大于设置在存储器模块上的端子电阻控制端子（ODT端子）的数量的情况下，也可以是封闭的端子电阻。 为此，在模块基板8上的数据总线19与数据输入/输出焊盘13之间具有较长互连长度的存储芯片12的端子电阻控制焊盘14连接到终端电阻控制互连 18或21以控制来自ODT端子的端子电阻的开/关。 在模块基板上的数据总线19与数据输入/输出焊盘13之间的互连的较短长度的存储芯片11上的端子电阻控制焊盘连接到固定电位20以接通端子电阻。
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公开(公告)号：US06046609A
公开(公告)日：2000-04-04
申请号：US188369
申请日：1998-11-10
申请人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
发明人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
IPC分类号： G11C11/419 , G11C7/06 , G11C11/409
CPC分类号： G11C7/065
摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being a 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
摘要翻译： 一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管 到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。 基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以降低输出响应的延迟时间。
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公开(公告)号：US5963483A
公开(公告)日：1999-10-05
申请号：US133952
申请日：1998-08-14
CPC分类号： G11C7/22 , G11C7/1072
摘要： A synchronous memory unit which includes a plurality of input buffers for receiving address data, a plurality of input latches for holding and outputting address data from in the input buffers according to a clock signal, a plurality of decoders for decoding the address data from the input latches, and a memory cell array having a plurality of memory cells which store and output data signals via bit lines according to the address data decoded by the decoders. Also provided are a sense amplifier for amplifying the output data signals on the bit lines, a selector for selecting one of the amplified output data signals according to the address data decoded by the decoders, and a selector output latch for holding and outputting the amplified output data signal from the selector according to the clock signal. An output latch holds and outputs the amplified output data signal from the selector output latch according to the clock signal. An output buffer receives and outputs the amplified output data signal from the output latch. Each latch includes a first latch for holding and outputting a data signal according to the clock signal, a first switch connected to the first latch for allowing a data signal to pass to the first latch according to the clock signal, and a second latch for holding and outputting a data signal according to the clock signal, and a second switch, connected between the first and second latches, for allowing a data signal to pass from the first latch to the second latch according to the clock signal.
摘要翻译： 一种同步存储单元，包括用于接收地址数据的多个输入缓冲器，用于根据时钟信号从输入缓冲器中保存和输出地址数据的多个输入锁存器，用于从输入端解码地址数据的多个解码器 锁存器和具有多个存储器单元的存储单元阵列，存储单元根据解码器解码的地址数据经由位线存储和输出数据信号。 还提供了用于放大位线上的输出数据信号的读出放大器，用于根据由解码器解码的地址数据来选择放大的输出数据信号之一的选择器，以及用于保存并输出放大的输出的选择器输出锁存器 来自选择器的数据信号根据时钟信号。 输出锁存器根据时钟信号保存并输出来自选择器输出锁存器的放大输出数据信号。 输出缓冲器从输出锁存器接收并输出放大的输出数据信号。 每个锁存器包括用于根据时钟信号保持和输出数据信号的第一锁存器，连接到第一锁存器的第一开关，用于根据时钟信号使数据信号传送到第一锁存器;以及第二锁存器，用于保持 并根据时钟信号输出数据信号，以及连接在第一和第二锁存器之间的第二开关，用于根据时钟信号允许数据信号从第一锁存器传递到第二锁存器。
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公开(公告)号：US06271687B1
公开(公告)日：2001-08-07
申请号：US09531530
申请日：2000-03-21
申请人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
发明人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
IPC分类号： G11C706
CPC分类号： G11C7/065
摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on a small voltage difference of input signals being amplified in two stages and the amplifying circuit being 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
摘要翻译： 一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管 到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。 基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以减少输出响应的延迟时间。
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