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    Apparatus having a wiring board and memory devices
    1.
    发明授权
    Apparatus having a wiring board and memory devices 有权
    具有接线板和存储器件的设备

    公开(公告)号：US08922029B2

    公开(公告)日：2014-12-30

    申请号：US13363396

    申请日：2012-02-01

    申请人： Atsushi Hiraishi ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

    发明人： Atsushi Hiraishi ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  G11C5/06 ,  G11C5/04 ,  G11C8/14 ,  H05K1/18

    CPC分类号： G11C5/063 ,  G11C5/04 ,  G11C8/14 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/10159 ,  Y02P70/611

    摘要： An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.

    摘要翻译： 具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。 数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。 从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。 从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。

    Address line wiring structure and printed wiring board having same
    2.
    发明授权
    Address line wiring structure and printed wiring board having same 有权
    地址线路布线结构和具有该布线结构的印刷布线板

    公开(公告)号：US08134239B2

    公开(公告)日：2012-03-13

    申请号：US12239900

    申请日：2008-09-29

    申请人： Atsushi Hiraishi ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

    发明人： Atsushi Hiraishi ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： G11C5/063 ,  G11C5/04 ,  G11C8/14 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/10159 ,  Y02P70/611

    摘要： An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.

    摘要翻译： 具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。 数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。 从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。 从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。

    ADDRESS LINE WIRING STRUCTURE AND PRINTED WIRING BOARD HAVING SAME
    3.
    发明申请
    ADDRESS LINE WIRING STRUCTURE AND PRINTED WIRING BOARD HAVING SAME 有权
    地线接线结构和印刷线路板

    公开(公告)号：US20090086522A1

    公开(公告)日：2009-04-02

    申请号：US12239900

    申请日：2008-09-29

    申请人： Atsushi HIRAISHI ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

    发明人： Atsushi HIRAISHI ,  Toshio Sugano ,  Masahiro Yamaguchi ,  Yoji Nishio ,  Tsutomu Hara ,  Koichiro Aoki

    IPC分类号： G11C5/06 ,  H05K1/18 ,  H05K7/00

    CPC分类号： G11C5/063 ,  G11C5/04 ,  G11C8/14 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/10159 ,  Y02P70/611

    摘要： An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.

    摘要翻译： 具有短截线结构的地址信号线连接在至少三个存储器元件和数据传输元件之间，并传送存储器元件的地址信号。 数据传送元件的地址端子的阻抗低于地址信号线的特性阻抗。 从数据传送元件到分支线从数据传送元件到最短距离分支的第一分支点S1的布线长度TL0被配置成等于或大于从第一分支点S1到布线长度TL1 第二分支点S2，其中第二支线被分支。 从第二分支点S2到分支第三分支线的第三分支点S3的布线长度TL3被配置为变得大于布线长度TL0和TL1。

    Stacked semiconductor device
    4.
    发明授权
    Stacked semiconductor device 有权
    堆叠半导体器件

    公开(公告)号：US07768867B2

    公开(公告)日：2010-08-03

    申请号：US11761470

    申请日：2007-06-12

    申请人： Yoji Nishio ,  Yutaka Uematsu ,  Seiji Funaba ,  Hideki Osaka ,  Tsutomu Hara ,  Koichiro Aoki

    发明人： Yoji Nishio ,  Yutaka Uematsu ,  Seiji Funaba ,  Hideki Osaka ,  Tsutomu Hara ,  Koichiro Aoki

    IPC分类号： G11C8/00

    CPC分类号： G11C7/02 ,  G11C5/02 ,  G11C5/04 ,  H01L25/105 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

    摘要： Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.

    摘要翻译： 叠层半导体器件包括多个存储器芯片，堆叠在一起，其中高速传输中的波形失真被去除。 堆叠半导体器件1包括堆叠在一起的多个存储器芯片11,12。 作为用于每周期两次输入/输出数据的控制信号的数据选通信号（DQS）和反相数据选通信号（/ DQS）被用作两个单端数据选通信号。 数据选通信号和反相数据选通信号相互配合。 用于数据选通信号L4的数据选通信号线连接到第一存储芯片11的数据选通信号（DQS）焊盘。用于/ DQS信号L5的反相数据选通信号线连接到第二存储芯片11的反相数据选通信号（/ DQS）焊盘 存储芯片12。

    Fish-gathering block
    6.
    发明授权
    Fish-gathering block 失效
    集鱼块

    公开(公告)号：US4165711A

    公开(公告)日：1979-08-28

    申请号：US802443

    申请日：1977-06-01

    申请人： Koichiro Aoki

    发明人： Koichiro Aoki

    IPC分类号： E02B3/04 ,  A01K61/00

    CPC分类号： E02B3/046

    摘要： A fish-gathering block comprising a plurality of supports erected on a base frame and supporting an upper structure. The current flows through an opening between the lower end of the upper structure and the base frame. This flowthrough opening prevents the sinking of the fish-gathering block into the sea-bottom by eliminating or materially weakening the ocean-current's excavating action.

    摘要翻译： 一种集合块，包括竖立在基架上并支撑上部结构的多个支撑件。 电流流过上结构的下端和基架之间的开口。 这个通风口通过消除或实质上削弱了海洋现象的挖掘作用，防止了集鱼块沉入海底。