公开(公告)号：US09171751B2

公开(公告)日：2015-10-27

申请号：US14264998

申请日：2014-04-29

申请人： AVOGY, INC.

发明人： Donald R. Disney ,  Andrew P. Edwards ,  Hui Nie ,  Richard J. Brown ,  Isik C. Kizilyalli ,  David P. Bour ,  Linda Romano ,  Thomas R. Prunty

IPC分类号： H01L29/06 ,  H01L21/761 ,  H01L21/266 ,  H01L21/265 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/808 ,  H01L29/872

CPC分类号： H01L21/761 ,  H01L21/2654 ,  H01L21/266 ,  H01L21/765 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66136 ,  H01L29/66212 ,  H01L29/6631 ,  H01L29/66909 ,  H01L29/8083 ,  H01L29/872

摘要： A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.

摘要翻译： 一种用于制造边缘终端结构的方法包括提供具有第一表面和第二表面和第一导电类型的衬底，形成耦合到衬底的第一表面的第一导电类型的第一GaN外延层，并形成第二 与第一导电类型相反的第二导电类型的GaN外延层。 第二GaN外延层耦合到第一GaN外延层。 该方法还包括将离子注入第二GaN外延层的第一区域以将第二GaN外延层的第二区域与第二GaN外延层的第三区域电隔离。 该方法还包括形成耦合到第二GaN外延层的第二区域并形成耦合到第二GaN外延层的第三区域的边缘端接结构的有源器件。

公开(公告)号：US20150179772A1

公开(公告)日：2015-06-25

申请号：US14489761

申请日：2014-09-18

申请人： Avogy, Inc.

发明人： Richard J. Brown ,  Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  David P. Bour

IPC分类号： H01L29/66 ,  H01L21/32 ,  H01L29/47 ,  H01L21/02 ,  H01L29/20 ,  H01L29/36

CPC分类号： H01L29/66856 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/32 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/475 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/8122

摘要： A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.

摘要翻译： 半导体结构包括III族氮化物衬底和沿生长方向耦合到III族氮化物衬底的漂移区域。 半导体衬底还包括耦合到漂移区的沟道区。 通道区域由基本沿着生长方向设置的通道侧壁限定。 半导体衬底还包括相对于沟道区域侧向设置的栅极区域。

公开(公告)号：US08941117B2

公开(公告)日：2015-01-27

申请号：US13935345

申请日：2013-07-03

申请人： Avogy, Inc.

发明人： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David P. Bour ,  Richard J. Brown ,  Thomas R. Prunty

IPC分类号： H01L31/0256 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/66 ,  H01L29/808 ,  H01L29/872 ,  H01L29/20 ,  H01L27/06 ,  H01L27/07 ,  H01L27/098

CPC分类号： H01L29/66909 ,  H01L21/823487 ,  H01L27/0605 ,  H01L27/0611 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/098 ,  H01L29/2003 ,  H01L29/66143 ,  H01L29/8083 ,  H01L29/872

摘要： An integrated device including a vertical III-nitride FET and a Schottky diode includes a drain comprising a first III-nitride material, a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, and a channel region comprising a third III-nitride material coupled to the drift region. The integrated device also includes a gate region at least partially surrounding the channel region, a source coupled to the channel region, and a Schottky contact coupled to the drift region. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride FET and the Schottky diode is along the vertical direction.

摘要翻译： 包括垂直III族氮化物FET和肖特基二极管的集成器件包括：包括第一III族氮化物材料的漏极，包括耦合到漏极并沿垂直方向邻近漏极设置的第二III族氮化物材料的漂移区， 以及包括耦合到所述漂移区的第三III族氮化物材料的沟道区。 集成器件还包括至少部分地围绕沟道区的栅极区域，耦合到沟道区的源极和耦合到漂移区域的肖特基接触。 沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直III族氮化物FET和肖特基二极管的工作期间的电流沿垂直方向。

公开(公告)号：US20150017792A1

公开(公告)日：2015-01-15

申请号：US14498916

申请日：2014-09-26

申请人： Avogy, Inc.

发明人： David P. Bour ,  Richard J. Brown ,  Isik C. Kizilyalli ,  Thomas R. Prunty ,  Linda Romano ,  Andrew P. Edwards ,  Hui Nie ,  Mahdan Raj

IPC分类号： H01L21/265 ,  H01L21/033 ,  H01L21/324 ,  H01L21/266

CPC分类号： H01L21/26546 ,  H01L21/0332 ,  H01L21/2258 ,  H01L21/266 ,  H01L21/3245 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.

摘要翻译： 在III族氮化物衬底中形成掺杂区域的方法包括提供III族氮化物衬底并形成具有预定图案并与III族氮化物衬底的一部分耦合的掩模层。 III族氮化物衬底的特征在于第一导电类型，并且预定图案限定III族氮化物衬底的暴露区域。 该方法还包括将III族氮化物衬底加热到​​预定温度，并将双前体气体放置在III族氮化物衬底的暴露区域附近。 双前体气体包括氮源和掺杂剂源。 该方法还包括将预定温度保持预定时间段，形成与III族氮化物衬底的暴露区域相邻的p型III族氮化物区域，以及去除掩模层。

公开(公告)号：US20140374769A1

公开(公告)日：2014-12-25

申请号：US14479634

申请日：2014-09-08

申请人： Avogy, Inc.

发明人： Richard J. Brown ,  Thomas R. Prunty ,  David P. Bour ,  Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  Madhan Raj

IPC分类号： H01L29/872 ,  H01L29/47 ,  H01L29/205 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/872 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/475 ,  H01L29/66143

摘要： A Schottky diode and method of fabricating the Schottky diode using gallium nitride (GaN) materials is disclosed. The method includes providing an n-type GaN substrate having first and second opposing surfaces. The method also includes forming an ohmic metal contact electrically coupled to the first surface, forming an n-type GaN epitaxial layer coupled to the second surface, and forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer. The AlGaN surface layer has a thickness which is less than a critical thickness, and the critical thickness is determined based on an aluminum mole fraction of the AlGaN surface layer. The method also includes forming a Schottky contact electrically coupled to the n-type AlGaN surface layer, where, during operation, an interface between the n-type GaN epitaxial layer and the n-type AlGaN surface layer is substantially free from a two-dimensional electron gas.

摘要翻译： 公开了肖特基二极管和使用氮化镓（GaN）材料制造肖特基二极管的方法。 该方法包括提供具有第一和第二相对表面的n型GaN衬底。 该方法还包括形成电耦合到第一表面的欧姆金属接触，形成耦合到第二表面的n型GaN外延层，以及形成与n型GaN结合的n型氮化镓铝（AlGaN）表面层 GaN外延层。 AlGaN表面层具有小于临界厚度的厚度，并且基于AlGaN表面层的铝摩尔分数来确定临界厚度。 该方法还包括形成电耦合到n型AlGaN表面层的肖特基接触，其中在操作期间，n型GaN外延层和n型AlGaN表面层之间的界面基本上不含二维 电子气。

公开(公告)号：US20140203328A1

公开(公告)日：2014-07-24

申请号：US14225334

申请日：2014-03-25

申请人： Avogy, Inc.

发明人： Donald R. Disney ,  Richard J. Brown ,  Hui Nie

IPC分类号： H01L29/808

CPC分类号： H01L29/8083 ,  H01L29/2003 ,  H01L29/66909

摘要： A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region.

摘要翻译： 半导体器件包括III族氮化物衬底和耦合到III族氮化物衬底并且包括漂移区，沟道区和延伸区的第一III族氮化物外延层。 沟道区域通过漂移区域与III族氮化物衬底分离。 通道区域的特征在于第一宽度。 延伸区域通过沟道区域与漂移区域分离。 延伸区域的特征在于小于第一宽度的第二宽度。 半导体器件还包括耦合到延伸区域的顶表面的第二III族氮化物外延层，耦合到沟道区域的侧壁并相对于延伸区域横向自对准的III族氮化物栅极结构，以及 栅极金属结构与III族氮化物栅极结构电接触并且相对于延伸区域横向自对准。

公开(公告)号：US20140191242A1

公开(公告)日：2014-07-10

申请号：US13735912

申请日：2013-01-07

申请人： AVOGY, INC.

发明人： Hui Nie ,  Andrew P. Edwards ,  Isik Kizilyalli ,  David P. Bour ,  Thomas R. Prunty ,  Quentin Diduck

IPC分类号： H01L29/66 ,  H01L29/808

CPC分类号： H01L29/66462 ,  H01L21/02389 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/122 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66909 ,  H01L29/66924 ,  H01L29/8083

摘要： A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.

摘要翻译： 垂直JFET包括包括JFET的漏极和耦合到GaN衬底的多个图案化外延层的GaN衬底。 远端外延层包括源通道的第一部分，并且相邻的图案化外延层被具有预定距离的间隙分开。 垂直JFET还包括耦合到远端外延层并且设置在间隙的至少一部分中的多个再生长的外延层。 近端再生长的外延层包括源通道的第二部分。 垂直JFET还包括通过远端再生长外延层的部分并与源极沟道电接触的源极接触，与远端再生长外延层电接触的栅极接触，以及与GaN衬底电接触的漏极接触 。

公开(公告)号：US20140159051A1

公开(公告)日：2014-06-12

申请号：US13935345

申请日：2013-07-03

申请人： AVOGY, INC.

发明人： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David P. Bour ,  Richard J. Brown ,  Thomas R. Prunty

IPC分类号： H01L29/808 ,  H01L27/06 ,  H01L29/20 ,  H01L29/66

CPC分类号： H01L29/66909 ,  H01L21/823487 ,  H01L27/0605 ,  H01L27/0611 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/098 ,  H01L29/2003 ,  H01L29/66143 ,  H01L29/8083 ,  H01L29/872

摘要： An integrated device including a vertical III-nitride FET and a Schottky diode includes a drain comprising a first III-nitride material, a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, and a channel region comprising a third III-nitride material coupled to the drift region. The integrated device also includes a gate region at least partially surrounding the channel region, a source coupled to the channel region, and a Schottky contact coupled to the drift region. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride FET and the Schottky diode is along the vertical direction.

摘要翻译： 包括垂直III族氮化物FET和肖特基二极管的集成器件包括：包括第一III族氮化物材料的漏极，包括耦合到漏极并沿垂直方向邻近漏极设置的第二III族氮化物材料的漂移区， 以及包括耦合到所述漂移区的第三III族氮化物材料的沟道区。 集成器件还包括至少部分地围绕沟道区的栅极区域，耦合到沟道区的源极和耦合到漂移区域的肖特基接触。 沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直III族氮化物FET和肖特基二极管的工作期间的电流沿垂直方向。

公开(公告)号：US20140051236A1

公开(公告)日：2014-02-20

申请号：US14062724

申请日：2013-10-24

申请人： AVOGY, INC.

发明人： Madhan Raj ,  Richard J. Brown ,  Thomas R. Prunty ,  David P. Bour ,  Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano

IPC分类号： H01L29/66

CPC分类号： H01L29/66143 ,  H01L29/0661 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66212 ,  H01L29/872

摘要： A method for fabricating a III-nitride semiconductor device includes providing a III-nitride substrate having a first surface and a second surface opposing the first surface, forming a III-nitride epitaxial layer coupled to the first surface of the III-nitride substrate, and removing at least a portion of the III-nitride epitaxial layer to form a first exposed surface. The method further includes forming a dielectric layer coupled to the first exposed surface, removing at least a portion of the dielectric layer, and forming a metallic layer coupled to a remaining portion of the dielectric layer such that the remaining portion of the dielectric layer is disposed between the III-nitride epitaxial layer and the metallic layer.

摘要翻译： 一种制造III族氮化物半导体器件的方法包括提供具有第一表面和与第一表面相对的第二表面的III族氮化物衬底，形成耦合到III族氮化物衬底的第一表面的III族氮化物外延层，以及 去除所述III族氮化物外延层的至少一部分以形成第一暴露表面。 该方法还包括形成耦合到第一暴露表面的电介质层，去除电介质层的至少一部分，以及形成耦合到电介质层的剩余部分的金属层，使得电介质层的剩余部分被布置 在III族氮化物外延层和金属层之间。

公开(公告)号：US09484470B2

公开(公告)日：2016-11-01

申请号：US14834306

申请日：2015-08-24

申请人： Avogy, Inc.

发明人： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Richard J. Brown ,  Donald R. Disney

IPC分类号： H01L29/868 ,  H01L29/06 ,  H01L21/20 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L29/868 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/66204 ,  H01L29/66212 ,  H01L29/6631 ,  H01L29/66924

摘要： A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region

摘要翻译： III族氮化物半导体器件包括用于在III族氮化物半导体器件的正向偏置操作期间支持电流的有源区域。 有源区包括具有第一导电类型的第一III族氮化物外延材料和具有第二导电类型的第二III族氮化物外延材料。 III族氮化物半导体器件还包括物理地邻近有源区的边缘终端区，并且包括包含第一III族氮化物外延材料的一部分的注入区。 第一III族氮化物外延材料的注入区域相对于邻近于注入区域的第一III族氮化物外延材料的部分具有降低的导电性