公开(公告)号：US06525589B1

公开(公告)日：2003-02-25

申请号：US09695705

申请日：2000-10-25

申请人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Aryesh Amar ,  Jerome E. Johnston

发明人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Aryesh Amar ,  Jerome E. Johnston

IPC分类号： H03K1716

CPC分类号： H03M3/494 ,  G01D3/022 ,  H03M3/448 ,  H03M3/452

摘要： An instrumentation circuit has an integrated circuit that has input terminals, an amplifier arrangement using feed forward compensation and an analog to digital converter and a serial data output receiving the output from said amplifier arrangement. A bridge circuit, having a transducer, or a thermocouple arrangement are connected to input terminals of the integrated circuit.

摘要翻译： 仪表电路具有具有输入端子的集成电路，使用前馈补偿的放大器装置和模数转换器以及接收来自所述放大器装置的输出的串行数据输出。 具有换能器或热电偶布置的桥式电路连接到集成电路的输入端子。

公开(公告)号：US06857002B1

公开(公告)日：2005-02-15

申请号：US09695704

申请日：2000-10-25

申请人： Axel Thomsen ,  Jerome E. Johnston ,  Edwin De Angel ,  Aryesh Amar

发明人： Axel Thomsen ,  Jerome E. Johnston ,  Edwin De Angel ,  Aryesh Amar

IPC分类号： G06F13/00 ,  G06F17/10 ,  H03H17/02 ,  H03M3/02

CPC分类号： H03H17/0294 ,  H03M3/392 ,  H03M3/462

摘要： In a signal processing integrated circuit having an analog to digital converter and a digital filter having a plurality of taps separated in time, when starting a conversion after a reset or a change of input channel, the filter will have an incomplete set of input data as the delayed inputs to an output calculation are all zero from the reset operation. After reset, during the time that data are filling up the filter pipeline, the calculation of an output value will give a result that holds information about the input, but does not present the data with the same scaling and frequency content as the fully settled filter. The integrated circuit selectively provides two modes, on that provides only fully settled data from the filter or and another that provides all data from the filter, including unsettled data. Knowledge about the filter coefficients can be utilized by a user or user process to extract information about the input from the unsettled data.

摘要翻译： 在具有模拟数字转换器的信号处理集成电路和具有时间分离的多个抽头的数字滤波器的情况下，当在复位或输入通道改变之后开始转换时，滤波器将具有不完整的输入数据集 输出计算的延迟输入从复位操作全部为零。 在复位之后，在数据填满过滤器管线的时间期间，输出值的计算将给出保存有关输入信息的结果，但不显示具有与完全设置的过滤器相同的缩放和频率内容的数据 。 集成电路有选择地提供两种模式，其中仅提供来自滤波器的完全确定的数据，或者提供来自滤波器的所有数据的另一种模式，包括不稳定的数据。 关于滤波器系数的知识可以由用户或用户进程利用来从未解决的数据中提取关于输入的信息。

公开(公告)号：US06891430B1

公开(公告)日：2005-05-10

申请号：US09695706

申请日：2000-10-25

申请人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Lei Wang ,  Aryesh Amar

发明人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Lei Wang ,  Aryesh Amar

IPC分类号： H03M3/00 ,  G06G7/12

CPC分类号： H03M3/494 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452

摘要： A signal processing integrated circuit has having a chopper stabilized, multistage, feedforward amplifier and a delta sigma analog to digital converter. Filtering of the output of the output from the analog to digital converter comprises a sinc5 filter and a sinc3 filter. The sinc3 filter may be bypassed. A rough buffer permits quick charging of a sample and hold capacitor during part of the charge cycle and slower but more accurate charging during the remainder of the charge cycle.

摘要翻译： 信号处理集成电路具有斩波稳定的多级前馈放大器和ΔΣ模数转换器。 从模数转换器输出的输出的滤波包括​​一个Sinc＆lt; 5＆gt;滤波器和一个sinc＆lt; 3＆gt; 3滤波器。 可以绕过sinc <3> 3滤波器。 一个粗略的缓冲器允许在充电周期的一部分期间快速充电一个采样和保持电容器，并且在充电周期的剩余时间内可以进行更慢但更精确的充电。

公开(公告)号：US07162506B1

公开(公告)日：2007-01-09

申请号：US11057450

申请日：2005-02-14

申请人： Axel Thomsen ,  Jerome E Johnston ,  Edwin Angel ,  Aryesh Amar

发明人： Axel Thomsen ,  Jerome E Johnston ,  Edwin Angel ,  Aryesh Amar

IPC分类号： G06F17/10

CPC分类号： H03H17/0294 ,  H03M3/392 ,  H03M3/462

摘要： In a signal processing integrated circuit having an analog to digital converter and a digital filter having a plurality of taps separated in time, when starting a conversion after a reset or a change of input channel, the filter will have an incomplete set of input data as the delayed inputs to an output calculation are all zero from the reset operation. After reset, during the time that data are filling up the filter pipeline, the calculation of an output value will give a result that holds information about the input, but does not present the data with the same scaling and frequency content as the fully settled filter. The integrated circuit selectively provides two modes, on that provides only fully settled data from the filter or and another that provides all data from the filter, including unsettled data. Knowledge about the filter coefficients can be utilized by a user or user process to extract information about the input from the unsettled data.

摘要翻译： 在具有模拟数字转换器的信号处理集成电路和具有时间分离的多个抽头的数字滤波器的情况下，当在复位或输入通道改变之后开始转换时，滤波器将具有不完整的输入数据集 输出计算的延迟输入从复位操作全部为零。 在复位之后，在数据填满过滤器管线的时间期间，输出值的计算将给出保存有关输入信息的结果，但不显示具有与完全设置的过滤器相同的缩放和频率内容的数据 。 集成电路有选择地提供两种模式，其中仅提供来自滤波器的完全确定的数据，或者提供来自滤波器的所有数据的另一种模式，包括不稳定的数据。 关于滤波器系数的知识可以由用户或用户进程利用来从未解决的数据中提取关于输入的信息。

公开(公告)号：US06885211B1

公开(公告)日：2005-04-26

申请号：US10117374

申请日：2002-04-05

申请人： Axel Thomsen ,  Sherry Wu ,  Murari Kejariwal ,  Ammisetti Prasad ,  John Laurence Melanson

发明人： Axel Thomsen ,  Sherry Wu ,  Murari Kejariwal ,  Ammisetti Prasad ,  John Laurence Melanson

IPC分类号： G01R31/28 ,  G01R31/26

CPC分类号： G01R31/2837

摘要： A method of testing an integrated circuit includes setting a guardbanded limit for a parameter associated with an embedded node, a deviation from the guardbanded limit under a set of test conditions correlated with a failure of the integrated circuit across a range of operating conditions. A test is performed under the test conditions to detect deviations of the parameter from the guardbanded limit to detect failures of the integrated circuit over the range of operating conditions.

摘要翻译： 一种测试集成电路的方法包括设置与嵌入式节点相关联的参数的保护限值，与在整个操作条件范围内的集成电路的故障相关的一组测试条件下的保护带限制的偏差。 在测试条件下进行测试，以检测参数与防护带限制的偏差，以检测集成电路在工作条件范围内的故障。

公开(公告)号：US08952751B2

公开(公告)日：2015-02-10

申请号：US13732135

申请日：2012-12-31

申请人： Axel Thomsen ,  Gang Yuan

发明人： Axel Thomsen ,  Gang Yuan

IPC分类号： H03F1/02 ,  H03F3/00 ,  H03F3/45

CPC分类号： H03F3/005 ,  H03F3/45197 ,  H03F3/45645 ,  H03F2203/45404 ,  H03F2203/45418 ,  H03F2203/45421 ,  H03F2203/45424 ,  H03F2203/45444 ,  H03F2203/45446 ,  H03F2203/45528 ,  H03F2203/45648

摘要： A method of operating an amplifier circuit having a pre-charge phase and a sample/conversion phase includes, during a pre-charge phase, charging first and second capacitors to first and second bias voltages. The first capacitor is coupled to a first input of an amplifier circuit, which has a second input and an output. The second capacitor is coupled to the second input. During a sample/conversion phase, the first input of the amplifier circuit is coupled to an input signal through the first capacitor to level-shift the input signal according to the first bias voltage and the output of the amplifier is coupled to the second input through the second capacitor to level shift a feedback signal according to the second bias voltage.

摘要翻译： 操作具有预充电阶段和采样/转换阶段的放大器电路的方法包括在预充电阶段期间将第一和第二电容器充电到第一和第二偏置电压。 第一电容器耦合到具有第二输入和输出的放大器电路的第一输入端。 第二电容器耦合到第二输入端。 在采样/转换阶段期间，放大器电路的第一输入通过第一电容耦合到输入信号，以根据第一偏置电压对输入信号进行电平移位，并且放大器的输出端通过 所述第二电容器根据所述第二偏置电压对反馈信号进行电平移位。

公开(公告)号：US20140176250A1

公开(公告)日：2014-06-26

申请号：US13721885

申请日：2012-12-20

申请人： Axel Thomsen ,  Pavel Konecny ,  Xiaodong Wang

发明人： Axel Thomsen ,  Pavel Konecny ,  Xiaodong Wang

IPC分类号： H03K3/011

CPC分类号： H03K3/0231

摘要： In an embodiment, a method includes: during a first portion of a cycle of a clock signal generated by an oscillator, pre-charging a first capacitor of a first switched capacitor stage until a first comparator determines that a first node voltage of the first switched capacitor stage is greater than a first reference voltage at a first reference voltage node; applying a second reference voltage to the first reference voltage node; and responsive to a first edge of the clock signal, charging the first capacitor until the first comparator determines that the first node voltage is greater than the second reference voltage at the first reference voltage node.

摘要翻译： 在一个实施例中，一种方法包括：在由振荡器产生的时钟信号的周期的第一部分期间，对第一开关电容器级的第一电容器进行预充电，直到第一比较器确定第一开关的第一节点电压 电容器级大于第一参考电压节点处的第一参考电压; 将第二参考电压施加到所述第一参考电压节点; 并且响应于所述时钟信号的第一边沿，对所述第一电容器充电直到所述第一比较器确定所述第一节点电压大于所述第一参考电压节点处的所述第二参考电压。

公开(公告)号：US08203370B2

公开(公告)日：2012-06-19

申请号：US12494621

申请日：2009-06-30

申请人： Shouli Yan ,  Zhiwei Dong ,  Axel Thomsen

发明人： Shouli Yan ,  Zhiwei Dong ,  Axel Thomsen

IPC分类号： H03K3/00

CPC分类号： H03K3/3565 ,  H03K5/088

摘要： A Schmitt trigger comprises first and second circuitry. The first circuitry receives an input voltage and provides an output voltage at either a logical “low” or a logical “high” voltage level responsive to the input voltage and a first bias voltage. The second circuitry connects to the first circuitry to generate a second bias current for generating the output voltage. The second bias current is larger than the first bias current. The Schmitt trigger operates in a low power mode of operation using only the first bias voltage to maintain the logical “low” voltage level or the logical “high” voltage level at a substantially constant level. In a high power mode of operation the Schmitt trigger uses the second bias voltage during transition periods between the logical “low” voltage level and the logical “high” voltage level.

摘要翻译： 施密特触发器包括第一和第二电路。 第一电路接收输入电压并且响应于输入电压和第一偏置电压在逻辑“低”或逻辑“高”电压电平提供输出电压。 第二电路连接到第一电路以产生用于产生输出电压的第二偏置电流。 第二偏置电流大于第一偏置电流。 施密特触发器仅在第一偏置电压下工作在低功耗工作模式，以将逻辑“低”电压电平或逻辑“高”电压电平维持在基本恒定的水平。 在高功率工作模式下，施密特触发器在逻辑“低”电压电平和逻辑“高”电压电平之间的过渡期间使用第二偏置电压。

公开(公告)号：US07834706B2

公开(公告)日：2010-11-16

申请号：US11571077

申请日：2005-06-28

申请人： Doug Frey ,  Axel Thomsen ,  Ligang Zhang

发明人： Doug Frey ,  Axel Thomsen ,  Ligang Zhang

IPC分类号： H03L7/00

CPC分类号： H03L7/0891 ,  H03L7/1976

摘要： A noise cancellation signal is generated for a fractional-N phase-locked loop (200). A divide value is provided to a first delta sigma modulator circuit (203), which generates a divide control signal to control a divide value of a feedback divider (208) in the phase-locked loop. An error term (e) is generated that is indicative of a difference between the generated divide control signal and the divide value supplied to the first delta sigma modulator circuit. The error term is integrated in an integrator (320) to generate an integrated error term (x), where xk+1=xk+ek; and a phase error correction circuit (209) utilizes the error term ek and the integrated error term xk to generate the phase error cancellation signal.

摘要翻译： 对于分数N锁相环（200）产生噪声消除信号。 分频值被提供给第一ΔΣ调制器电路（203），其产生除法控制信号以控制锁相环中的反馈分频器（208）的除法值。 生成指示所生成的除法控制信号和提供给第一ΔΣ调制器电路的除法值之间的差异的误差项（e）。 误差项集成在积分器（320）中以产生积分误差项（x），其中xk + 1 = xk + ek; 并且相位误差校正电路（209）利用误差项ek和积分误差项xk来产生相位误差消除信号。

公开(公告)号：US07295077B2

公开(公告)日：2007-11-13

申请号：US11270954

申请日：2005-11-10

申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein ,  Michael Petrowski, III

发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein ,  Michael Petrowski, III

IPC分类号： H03B21/00

CPC分类号： H03L7/23 ,  H03L7/0898 ,  H03L7/197 ,  H03L7/1976

摘要： A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.

摘要翻译： 锁相环（PLL）电路包括用于接收定时参考信号的输入端，耦合以接收定时参考信号的相位检测器电路，根据相位检测器电路的输出控制的可控振荡器电路，以及反馈分配器 电路具有耦合到相位检测器的输出端和耦合到可控振荡器电路的输入端。 锁相环电路根据频率选择机构耦合到输出具有任意频率关系的多个输出信号中的一个，所述频率选择机构包括一个或多个输入端，用于控制所述频率选择机构的分频比 反馈分频电路。 频率选择机构选择多个存储值中的一个。 选择的存储值至少部分地控制反馈分频器电路的分频比，从而提供能够在彼此具有任意关系的输出频率之间进行选择的引脚可编程器件。