公开(公告)号：US07288998B2

公开(公告)日：2007-10-30

申请号：US11270957

申请日：2005-11-10

申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein ,  Derrick C. Wei

发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein ,  Derrick C. Wei

IPC分类号： H03L7/00

CPC分类号： H03L7/0898 ,  H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/197 ,  H03L7/1976 ,  H03L7/23 ,  H03L7/235 ,  H03L2207/50 ,  H04J3/0688

摘要： A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillator output signal. The frequency of the oscillator output signal is determined in part according to a stored value used to generate a first digital control signal that determines a divide ratio of the feedback divider circuit. A control voltage present on a voltage control input adjusts the frequency of the oscillator output signal around a frequency determined by the stored value. The control voltage is converted to second digital signal and is utilized in determining the first digital control signal in combination with the stored value.

摘要翻译： 电压控制时钟合成器包括接收定时参考信号的锁相环（PLL）电路，提供振荡器输出信号的可控振荡器电路，例如VCO，以及耦合到振荡器输出信号的反馈分频器电路。 振荡器输出信号的频率部分地根据用于产生确定反馈分频器电路的分频比的第一数字控制信号的存储值来确定。 存在于电压控制输入端的控制电压根据由存储的值确定的频率调整振荡器输出信号的频率。 控制电压被转换为第二数字信号，并用于与所存储的值组合确定第一数字控制信号。

公开(公告)号：US07141883B2

公开(公告)日：2006-11-28

申请号：US10463961

申请日：2003-06-18

申请人： Derrick C. Wei ,  Ying Shi ,  Kevin G. Smith ,  Steven P. Proffitt ,  Axel Thomsen ,  David M. Pietruszynski ,  Ligang Zhang

发明人： Derrick C. Wei ,  Ying Shi ,  Kevin G. Smith ,  Steven P. Proffitt ,  Axel Thomsen ,  David M. Pietruszynski ,  Ligang Zhang

IPC分类号： H01L23/48 ,  H01L23/552

CPC分类号： H01L23/552 ,  H01F2017/008 ,  H01L23/645 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2224/0401

摘要： An electromagnetically-shielded high-Q inductor may be fabricated within a multi-layer package substrate (MLS). The inductor is preferably constructed as a loop structure on a layer of the MLS, and a shielding structure is formed around the inductor to substantially enclose the inductor in a Faraday cage-like enclosure. The shielding structure includes a top plate formed above the inductor on another layer of the MLS, and a bottom plate formed on yet another layer of the MLS or on a layer of an integrated circuit die which is below and attached to the MLS, preferably using solder bumps. Shielding structure sidewalls may be formed by a ring of stacked vias or via channels. The inductor is preferably connected to stacked vias which provide a connection to the underlying integrated circuit die by way of additional solder bumps and cut-outs through the bottom plate of the shielding structure.

摘要翻译： 可以在多层封装衬底（MLS）内制造电磁屏蔽的高Q电感器。 电感器优选地构造为MLS层上的环路结构，并且围绕电感器形成屏蔽结构，以将电感器基本上包围在法拉第笼状壳体中。 屏蔽结构包括在MLS的另一层上形成在电感器上方的顶板，以及形成在MLS的另一层上的底板或集成电路管芯的下面并连接到MLS上的层，优选地使用 焊锡凸块 屏蔽结构侧壁可以由堆叠的通孔环或通孔形成。 电感器优选地连接到堆叠的通孔，其通过附加的焊料凸块和穿过屏蔽结构的底板的切口提供到下面的集成电路管芯的连接。

公开(公告)号：US07199641B2

公开(公告)日：2007-04-03

申请号：US11172446

申请日：2005-06-30

申请人： Derrick C. Wei

发明人： Derrick C. Wei

IPC分类号： H03K17/687

CPC分类号： H02M3/073 ,  H02M2001/009

摘要： A technique implements high impedance nodes using high threshold voltage devices that may generate less leakage current and may have a higher gate oxide breakdown voltage than standard devices in a particular manufacturing technology. Under at least one operating condition, for a particular power supply voltage, a circuit may unable to produce a control signal that is sufficient to turn on such a high threshold voltage device. The technique adjusts the control signal voltage to provide a gate-to-source voltage sufficient to turn on the high threshold voltage device. At another power supply voltage, when the circuit is able to produce a control signal sufficient to turn on the high threshold voltage device, the technique does not adjust the control signal.