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公开(公告)号：US20080288780A1
公开(公告)日：2008-11-20
申请号：US12142007
申请日：2008-06-19
申请人： BRUCE L. BEUKEMA , Robert A. Drehmel , William E. Hall , Jamie R. Kuesel , Gilad Pivonia , Robert A. Shearer
发明人： BRUCE L. BEUKEMA , Robert A. Drehmel , William E. Hall , Jamie R. Kuesel , Gilad Pivonia , Robert A. Shearer
IPC分类号： H04L9/00
CPC分类号： G06F21/72 , H04L9/06 , H04L63/123 , H04L2209/125
摘要： Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of encrypted data is validated (e.g., by checking for data transfer errors), the encrypted data may be pipelined to a decryption engine as it is received, thus allowing decryption to begin prior to validation. In some cases, the decryption engine may be notified of data transfer errors detected during the validation process, in order to prevent reporting false security violations.
摘要翻译： 提供了减少与解密加密数据相关的延迟的影响的方法和装置。 而不是等到整个加密数据包被验证（例如，通过检查数据传输错误），加密的数据可以在被接收时被流水线化到解密引擎，从而允许在验证之前开始解密。 在一些情况下，可以向解密引擎通知在验证过程期间检测到的数据传输错误，以防止报告错误的安全违规。
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公开(公告)号：US08069353B2
公开(公告)日：2011-11-29
申请号：US12142007
申请日：2008-06-19
申请人： Bruce L. Beukema , Robert A. Drehmel , William E. Hall , Jamie R. Kuesel , Gilad Pivonia , Robert A. Shearer
发明人： Bruce L. Beukema , Robert A. Drehmel , William E. Hall , Jamie R. Kuesel , Gilad Pivonia , Robert A. Shearer
IPC分类号： H04L9/32
CPC分类号： G06F21/72 , H04L9/06 , H04L63/123 , H04L2209/125
摘要： Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of encrypted data is validated (e.g., by checking for data transfer errors), the encrypted data may be pipelined to a decryption engine as it is received, thus allowing decryption to begin prior to validation. In some cases, the decryption engine may be notified of data transfer errors detected during the validation process, in order to prevent reporting false security violations.
摘要翻译： 提供了减少与解密加密数据相关的延迟的影响的方法和装置。 而不是等到整个加密数据包被验证（例如，通过检查数据传输错误），加密的数据可以在被接收时被流水线化到解密引擎，从而允许在验证之前开始解密。 在一些情况下，可以向解密引擎通知在验证过程期间检测到的数据传输错误，以防止报告错误的安全违规。
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公开(公告)号：US07409558B2
公开(公告)日：2008-08-05
申请号：US10932727
申请日：2004-09-02
申请人： Bruce L. Beukema , Robert A. Drehmel , William E. Hall , Jamie R. Kuesel , Gilad Pivonia , Robert A. Shearer
发明人： Bruce L. Beukema , Robert A. Drehmel , William E. Hall , Jamie R. Kuesel , Gilad Pivonia , Robert A. Shearer
IPC分类号： H04L9/00
CPC分类号： G06F21/72 , H04L9/06 , H04L63/123 , H04L2209/125
摘要： Methods and apparatus for reducing the impact of latency associated with decrypting encrypted data are provided. Rather than wait until an entire packet of encrypted data is validated (e.g., by checking for data transfer errors), the encrypted data may be pipelined to a decryption engine as it is received, thus allowing decryption to begin prior to validation. In some cases, the decryption engine may be notified of data transfer errors detected during the validation process, in order to prevent reporting false security violations.
摘要翻译： 提供了减少与解密加密数据相关的延迟的影响的方法和装置。 而不是等到整个加密数据包被验证（例如，通过检查数据传输错误），加密的数据可以在被接收时被流水线化到解密引擎，从而允许在验证之前开始解密。 在一些情况下，可以向解密引擎通知在验证过程期间检测到的数据传输错误，以防止报告错误的安全违规。
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4.发明申请DATA ENCRYPTION INTERFACE FOR REDUCING ENCRYPT LATENCY IMPACT ON STANDARD TRAFFIC 审中-公开数据加密接口减少加密对标准交通的影响公开(公告)号：US20090144564A1
公开(公告)日：2009-06-04
申请号：US12364610
申请日：2009-02-03
IPC分类号： H04L9/06
摘要： Methods and apparatus that may be utilized in systems to reduce the impact of latency associated with encrypting data on non-encrypted data are provided. Secure and non-secure data may be routed independently. Thus, non-secure data may be forwarded on (e.g., to targeted write buffers), without waiting for previously sent secure data to be encrypted. As a result, non-secure data may be made available for subsequent processing much earlier than in conventional systems utilizing a common data path for both secure and non-secure data.
摘要翻译： 提供了可以在系统中用于减少与未加密数据加密数据相关的延迟的影响的方法和装置。 安全和非安全数据可以独立路由。 因此，非安全数据可以被转发（例如，到目标写缓冲器），而不等待先前发送的安全数据被加密。 因此，与使用用于安全和非安全数据的公共数据路径的常规系统相比，非安全数据可能比后续处理可用。
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公开(公告)号：US07660247B2
公开(公告)日：2010-02-09
申请号：US12018226
申请日：2008-01-23
CPC分类号： G06F13/4208
摘要： Methods and systems for dynamically adjusting credits used to distribute available bus bandwidth among multiple virtual channels, based on the workload of each virtual channel, are provided. Accordingly, for some embodiments, virtual channels with higher workloads relative to other virtual channels may receive a higher allocation of bus bandwidth (more credits).
摘要翻译： 提供了基于每个虚拟通道的工作负载动态调整用于在多个虚拟通道中分配可用总线带宽的信用的方法和系统。 因此，对于一些实施例，相对于其他虚拟信道具有较高工作负载的虚拟信道可以接收更高的总线带宽分配（更多信用）。
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公开(公告)号：US07362705B2
公开(公告)日：2008-04-22
申请号：US10845497
申请日：2004-05-13
CPC分类号： G06F13/4208
摘要： Methods and systems for dynamically adjusting credits used to distribute available bus bandwidth among multiple virtual channels, based on the workload of each virtual channel, are provided. Accordingly, for some embodiments, virtual channels with higher workloads relative to other virtual channels may receive a higher allocation of bus bandwidth (more credits).
摘要翻译： 提供了基于每个虚拟通道的工作负载动态调整用于在多个虚拟通道中分配可用总线带宽的信用的方法和系统。 因此，对于一些实施例，相对于其他虚拟信道具有较高工作负载的虚拟信道可以接收更高的总线带宽分配（更多信用）。
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7.发明授权公开(公告)号：US07840757B2
公开(公告)日：2010-11-23
申请号：US10901600
申请日：2004-07-29
申请人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer , Bruce M. Walk
发明人： Bruce L. Beukema , Russell D. Hoover , Jon K. Kriegel , Jamie R. Kuesel , Eric O. Mejdrich , Robert A. Shearer , Bruce M. Walk
IPC分类号： G06F12/00
CPC分类号： G06F12/0888
摘要： Computer systems with direct updating of cache (e.g., primary L1 cache) memories of a processor, such as a central processing unit (CPU) or graphics processing unit (GPU). Special addresses are reserved for high speed memory. Memory access requests involving these reserved addresses are routed directly to the high speed memory. Memory access requests not involving these reserved addresses are routed to memory external to the processor.
摘要翻译： 具有直接更新诸如中央处理单元（CPU）或图形处理单元（GPU）的处理器的高速缓存（例如，主要L1高速缓存）存储器的计算机系统。 专用地址保留给高速存储器。 涉及这些保留地址的存储器访问请求直接路由到高速存储器。 不涉及这些保留地址的存储器访问请求被路由到处理器外部的存储器。
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8.发明授权Data encryption interface for reducing encrypt latency impact on standard traffic 失效数据加密接口，用于减少加密延迟对标准流量的影响公开(公告)号：US07496753B2
公开(公告)日：2009-02-24
申请号：US10932943
申请日：2004-09-02
IPC分类号： G06F9/00
摘要： Methods and apparatus that may be utilized in systems to reduce the impact of latency associated with encrypting data on non-encrypted data are provided. Secure and non-secure data may be routed independently. Thus, non-secure data may be forwarded on (e.g., to targeted write buffers), without waiting for previously sent secure data to be encrypted. As a result, non-secure data may be made available for subsequent processing much earlier than in conventional systems utilizing a common data path for both secure and non-secure data.
摘要翻译： 提供了可以在系统中用于减少与未加密数据加密数据相关的延迟的影响的方法和装置。 安全和非安全数据可以独立路由。 因此，非安全数据可以被转发（例如，到目标写缓冲器），而不等待先前发送的安全数据被加密。 因此，与使用用于安全和非安全数据的公共数据路径的常规系统相比，非安全数据可能比后续处理可用。
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公开(公告)号：US09176885B2
公开(公告)日：2015-11-03
申请号：US13355613
申请日：2012-01-23
CPC分类号： G06F12/0888 , G06F13/28
摘要： A circuit arrangement and method utilize cache injection logic to perform a cache inject and lock operation to inject a cache line in a cache memory and automatically lock the cache line in the cache memory in parallel with communication of the cache line to a main memory. The cache injection logic may additionally limit the maximum number of locked cache lines that may be stored in the cache memory, e.g., by aborting a cache inject and lock operation, injecting the cache line without locking, or unlocking and/or evicting another cache line in the cache memory.
摘要翻译： 电路装置和方法利用高速缓存注入逻辑来执行高速缓存注入和锁定操作，以将高速缓存行注入到高速缓冲存储器中，并且将高速缓存行与高速缓存行的通信并行地主动地锁定在高速缓存存储器中。 高速缓存注入逻辑可以另外限制可以存储在高速缓冲存储器中的锁定高速缓存行的最大数量，例如通过中止高速缓存注入和锁定操作，在不锁定的情况下注入高速缓存行，或者解锁和/或驱逐另一个高速缓存行 在缓存中。
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公开(公告)号：US07884819B2
公开(公告)日：2011-02-08
申请号：US11535581
申请日：2006-09-27
IPC分类号： G06T15/50
摘要： By merging or adding the color contributions from objects intersected by secondary rays, the image processing system may accumulate color contributions to pixels from objects intersected by secondary rays as the further color contributions are determined. Furthermore, by associating a scaling factor of color contribution with objects and with secondary rays which intersect the objects, color contributions due to secondary ray/object intersections may be calculated at a later time than the color contribution to a pixel from original ray/object intersection. Consequently, it is not necessary for a vector throughput engine or a workload manager to wait for all secondary ray/object intersections to be determined before updating the color of a pixel.
摘要翻译： 通过合并或添加由二次光线相交的物体的颜色贡献，图像处理系统可以累积对由二次光线相交的物体的像素的颜色贡献，因为确定了另外的颜色贡献。 此外，通过将颜色贡献的缩放因子与对象相交，并且与与对象相交的次要光线相关联，可以在比从原始光线/物体交叉点对像素的颜色贡献更晚的时间来计算由于次级光线/物体交叉点引起的颜色贡献 。 因此，在更新像素的颜色之前，矢量吞吐量引擎或工作负载管理器不必等待所有二次光线/物体交叉点的确定。
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