公开(公告)号：US20110176375A1

公开(公告)日：2011-07-21

申请号：US12984342

申请日：2011-01-04

申请人： Beom-seop Lee ,  Young-hyun Jun ,  Sang-joon Hwang

发明人： Beom-seop Lee ,  Young-hyun Jun ,  Sang-joon Hwang

IPC分类号： G11C7/00 ,  G11C8/08

CPC分类号： G11C7/02 ,  G11C7/222 ,  G11C8/08 ,  G11C8/14 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4099 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10897

摘要： A semiconductor memory device for reducing ripple noise of a back-bias voltage, and a method of driving the semiconductor memory device include a word line driving circuit and a delay logic circuit. The word line driving circuit enables a sub-word line connected to a selected memory cell to a first voltage, and disables the sub-word line of a non-selected memory cell to a second voltage and a third voltage, in response to a sub-word line enable signal, a first word line driving signal, and a second word line driving signal. The delay logic circuit controls the semiconductor memory device so that an amount of charge of the sub-word line that is introduced to the third voltage is greater than an amount of charge of the sub-word line that is introduced to the second voltage by changing a transition point of time of the sub-word line enable signal with respect to a transition point of time of the first word line driving signal, during the disabling of the sub-word line.

摘要翻译： 一种用于减小背偏电压的纹波噪声的半导体存储器件，以及驱动该半导体存储器件的方法包括字线驱动电路和延迟逻辑电路。 字线驱动电路使得连接到所选择的存储单元的子字线成为第一电压，并且响应于子级驱动电路将子选择的非选择存储单元的子字线禁止为第二电压和第三电压 第一字线驱动信号和第二字线驱动信号。 延迟逻辑电路控制半导体存储器件，使得被引入到第三电压的子字线的电荷量大于通过改变引入到第二电压的子字线的电荷量 在子字线禁用期间相对于第一字线驱动信号的转变点的子字线使能信号的转变时间点。

公开(公告)号：US08379476B2

公开(公告)日：2013-02-19

申请号：US12984342

申请日：2011-01-04

申请人： Beom-seop Lee ,  Young-hyun Jun ,  Sang-joon Hwang

发明人： Beom-seop Lee ,  Young-hyun Jun ,  Sang-joon Hwang

IPC分类号： G11C8/00 ,  G11C5/14 ,  G11C7/00

CPC分类号： G11C7/02 ,  G11C7/222 ,  G11C8/08 ,  G11C8/14 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4099 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10897

摘要： A semiconductor memory device for reducing ripple noise of a back-bias voltage, and a method of driving the semiconductor memory device include a word line driving circuit and a delay logic circuit. The word line driving circuit enables a sub-word line connected to a selected memory cell to a first voltage, and disables the sub-word line of a non-selected memory cell to a second voltage and a third voltage, in response to a sub-word line enable signal, a first word line driving signal, and a second word line driving signal. The delay logic circuit controls the semiconductor memory device so that an amount of charge of the sub-word line that is introduced to the third voltage is greater than an amount of charge of the sub-word line that is introduced to the second voltage by changing a transition point of time of the sub-word line enable signal with respect to a transition point of time of the first word line driving signal, during the disabling of the sub-word line.

摘要翻译： 一种用于减小背偏电压的纹波噪声的半导体存储器件，以及驱动该半导体存储器件的方法包括字线驱动电路和延迟逻辑电路。 字线驱动电路使得连接到所选择的存储单元的子字线成为第一电压，并且响应于子级驱动电路将子选择的非选择存储单元的子字线禁止为第二电压和第三电压 第一字线驱动信号和第二字线驱动信号。 延迟逻辑电路控制半导体存储器件，使得被引入到第三电压的子字线的电荷量大于通过改变引入到第二电压的子字线的电荷量 在子字线禁用期间相对于第一字线驱动信号的转变点的子字线使能信号的转变时间点。

公开(公告)号：US08638621B2

公开(公告)日：2014-01-28

申请号：US13413938

申请日：2012-03-07

申请人： Jong-pil Son ,  Chul-woo Park ,  Young-hyun Jun ,  Hong-sun Hwang ,  Hak-soo Yu

发明人： Jong-pil Son ,  Chul-woo Park ,  Young-hyun Jun ,  Hong-sun Hwang ,  Hak-soo Yu

IPC分类号： G11C7/00 ,  G11C11/419

CPC分类号： G11C11/419 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.

摘要翻译： 一种半导体存储器件，包括连接到存储单元的位线和被配置为响应于位线的电压电平驱动全局位线的电压电平的读出放大器。 感测放大器提供与存储在存储器单元中的数据互补的数据到全局位线，并且在存储器单元的有效操作期间将全局位线的互补数据提供给存储单元。

公开(公告)号：US20120230139A1

公开(公告)日：2012-09-13

申请号：US13413938

申请日：2012-03-07

申请人： Jong-pil Son ,  Chul-woo Park ,  Young-hyun Jun ,  Hong-sun Hwang ,  Hak-soo Yu

发明人： Jong-pil Son ,  Chul-woo Park ,  Young-hyun Jun ,  Hong-sun Hwang ,  Hak-soo Yu

IPC分类号： G11C7/06 ,  G11C7/12

CPC分类号： G11C11/419 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.

摘要翻译： 一种半导体存储器件，包括连接到存储单元的位线和被配置为响应于位线的电压电平驱动全局位线的电压电平的读出放大器。 感测放大器提供与存储在存储器单元中的数据互补的数据到全局位线，并且在存储器单元的有效操作期间将全局位线的互补数据提供给存储单元。

公开(公告)号：US07928795B2

公开(公告)日：2011-04-19

申请号：US12458533

申请日：2009-07-15

申请人： Joung-yeal Kim ,  Young-hyun Jun ,  Bai-sun Kong

发明人： Joung-yeal Kim ,  Young-hyun Jun ,  Bai-sun Kong

IPC分类号： G05F1/10

CPC分类号： H02M3/07

摘要： Provided is a semiconductor device for performing charge pumping. The semiconductor device may include a first pumping unit, a second pumping unit, and a controller. The first pumping unit may be configured to output a boosted voltage via an output node by using a first input signal and the initial voltage, where the boosted voltage is greater than an initial voltage. The second pumping unit may be configured to output the boosted voltage via the output node by using a second input signal and the initial voltage. The controller may be configured to control the first and second pumping units. Each of the first and second pumping units may include an initialization unit, a boosting unit, and a transmission unit. The initialization unit may be configured to control a voltage of a boosting node to be equal to the initial voltage during an initialization operation. The boosting unit may be configured to boost the voltage of the boosting node based on the first and second input signals. Also, the transmission unit may be configured to control output of the boosted voltage.

摘要翻译： 提供一种用于进行电荷泵送的半导体器件。 半导体器件可以包括第一泵送单元，第二泵送单元和控制器。 第一泵单元可以被配置为通过使用第一输入信号和初始电压经由输出节点输出升压电压，其中升压电压大于初始电压。 第二泵送单元可以被配置为通过使用第二输入信号和初始电压经由输出节点输出升压电压。 控制器可以被配置为控制第一和第二泵送单元。 第一和第二泵送单元中的每一个可以包括初始化单元，升压单元和传输单元。 初始化单元可以被配置为在初始化操作期间将升压节点的电压控制为等于初始电压。 升压单元可以被配置为基于第一和第二输入信号来升压升压节点的电压。 此外，传输单元可以被配置为控制升压电压的输出。

公开(公告)号：US20120099389A1

公开(公告)日：2012-04-26

申请号：US13236972

申请日：2011-09-20

申请人： Chul-woo PARK ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

发明人： Chul-woo PARK ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

IPC分类号： G11C11/402 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/808 ,  G06F2213/0038 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/40626 ,  G11C2211/4062

摘要： A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.

摘要翻译： 存储器模块可以包括多个动态存储器设备，每个动态存储器设备可以包括其中具有其中各自区域的动态存储器单元阵列，其中多个动态存储器设备可被配置为响应于命令操作相应的区域。 DRAM管理单元可以在模块上并且耦合到多个动态存储器设备，并且可以包括存储器设备操作参数存储电路，其被配置为存储用于各个区域的存储器设备操作参数以影响相应区域的操作 命令。

公开(公告)号：US20100045491A1

公开(公告)日：2010-02-25

申请号：US12547204

申请日：2009-08-25

申请人： Seung-jun Bae ,  Young-hyun Jun ,  Joo-sun Choi ,  Kwang-il Park ,  Sang-hyup Kwak

发明人： Seung-jun Bae ,  Young-hyun Jun ,  Joo-sun Choi ,  Kwang-il Park ,  Sang-hyup Kwak

IPC分类号： H03M7/00

CPC分类号： H03M5/06 ,  G11C7/1006

摘要： An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.

摘要翻译： 输入/输出（IO）接口包括数据编码器，其对具有不同定时的多个并行数据中的每一个进行编码并生成多个编码数据;以及交流（AC）耦合传输单元，其传输多个 的交流耦合方法中的编码数据。 数据编码器在逐位的基础上将第一并行数据与多条并行数据中的第二并行数据进行比较，并且获得其逻辑状态已经在第一并行数据和第二并行数据之间转移的位数。 当逻辑状态已经转移的位数大于或等于参考位数时，数据编码器反转第二并行数据的位值，以产生编码数据。 当逻辑状态已经转移的位数小于参考位数时，数据编码器维持第二并行数据的位值以产生编码数据。

公开(公告)号：US07589580B2

公开(公告)日：2009-09-15

申请号：US11797865

申请日：2007-05-08

申请人： Ho-suk Lee ,  Jae-goo Lee ,  Young-hyun Jun

发明人： Ho-suk Lee ,  Jae-goo Lee ,  Young-hyun Jun

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： Provided are a reference current generating method and a current reference circuit. The reference current generating method includes generating a first current using a NMOS transistor and a second current using a PMOS transistor, calculating a current difference between the first and second currents, generating a third current which has a similar current/temperature slope as the second current by multiplying the current difference by a proportional constant, and generating a reference current by subtracting the third current from the second current.

摘要翻译： 提供了参考电流产生方法和电流参考电路。 参考电流产生方法包括使用NMOS晶体管产生第一电流和使用PMOS晶体管产生第二电流，计算第一和第二电流之间的电流差，产生具有与第二电流相似的电流/温度斜率的第三电流 通过将电流差乘以比例常数，并通过从第二电流减去第三电流来产生参考电流。

公开(公告)号：US20070273352A1

公开(公告)日：2007-11-29

申请号：US11797865

申请日：2007-05-08

申请人： Ho-suk Lee ,  Jae-goo Lee ,  Young-hyun Jun

发明人： Ho-suk Lee ,  Jae-goo Lee ,  Young-hyun Jun

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： Provided are a reference current generating method and a current reference circuit. The reference current generating method includes generating a first current using a NMOS transistor and a second current using a PMOS transistor, calculating a current difference between the first and second currents, generating a third current which has a similar current/temperature slope as the second current by multiplying the current difference by a proportional constant, and generating a reference current by subtracting the third current from the second current.

摘要翻译： 提供了参考电流产生方法和电流参考电路。 参考电流产生方法包括使用NMOS晶体管产生第一电流和使用PMOS晶体管产生第二电流，计算第一和第二电流之间的电流差，产生具有与第二电流相似的电流/温度斜率的第三电流 通过将电流差乘以比例常数，并通过从第二电流减去第三电流来产生参考电流。

公开(公告)号：US20110126039A1

公开(公告)日：2011-05-26

申请号：US12950028

申请日：2010-11-19

申请人： Si-hong Kim ,  Young-hyun Jun ,  Kwnag-II Park

发明人： Si-hong Kim ,  Young-hyun Jun ,  Kwnag-II Park

IPC分类号： G06F1/06 ,  G11C7/22

CPC分类号： G11C7/225 ,  G06F1/06 ,  G11C7/02 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

摘要： A memory device comprising: at least one bank of memory cells that receives a first clock for clocking commands and a second clock for clocking data, wherein the second clock is activated based on a first command and deactivated based on a second command. The memory device further including a clock activation circuit configured to generate an enable signal based on the first command and a disable signal based on the second command, and a clock generator configured to generate the second clock based on a reference clock upon receipt of the enable signal.

摘要翻译： 一种存储器件，包括：至少一组存储器单元，其接收用于计时命令的第一时钟和用于计时数据的第二时钟，其中所述第二时钟基于第一命令而被激活，并且基于第二命令被去激活。 所述存储装置还包括时钟激活电路，所述时钟激活电路经配置以基于所述第一命令生成使能信号和基于所述第二命令的禁用信号;以及时钟发生器，被配置为在接收到所述使能时基于参考时钟生成所述第二时钟 信号。