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公开(公告)号:US4969979A
公开(公告)日:1990-11-13
申请号:US348844
申请日:1989-05-08
申请人: Bernd K. Appelt , Perminder Bindra , Robert D. Edwards , James R. Loomis , Jae M. Park , Jonathan D. Reid , Lisa J. Smith , James R. White
发明人: Bernd K. Appelt , Perminder Bindra , Robert D. Edwards , James R. Loomis , Jae M. Park , Jonathan D. Reid , Lisa J. Smith , James R. White
CPC分类号: C25D5/56 , H05K3/424 , H05K2203/0716 , H05K2203/122 , H05K3/427
摘要: Substantially nonconductive or semiconductive surfaces of through holes can be electroplated directly, without an intervening non-electrolytic metallization, by a stepwise process which includes the application to the through holes of a polyelectrolyte surfactant in solution in combination with the application of a conductive metal containing material.
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公开(公告)号:US5421507A
公开(公告)日:1995-06-06
申请号:US134994
申请日:1993-10-12
IPC分类号: H01R43/02 , B23K35/00 , B23K35/30 , H01R4/02 , H05K3/28 , H05K3/32 , H05K3/40 , H05K3/46 , B23K1/00
CPC分类号: B23K35/3013 , B23K35/001 , H01R4/02 , H05K3/4614 , H01L2924/0132 , H05K2201/0305 , H05K3/28 , H05K3/328 , H05K3/4038 , Y10S428/901 , Y10T156/1056 , Y10T29/49126
摘要: A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au--Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, mulilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.
摘要翻译: 公开了一种同时层压电路化电介质层以形成多层高性能电路板并制造层间电连接的方法。 该方法选择将在一个低温下形成共晶体的两种元素,并将固化形成合金,该合金将仅在任何后续层压所要求的第二温度下再熔化。 使用瞬态液体粘合技术和足够的Au和Sn制成接头,以在低温下产生Au-Sn20wt%共晶。 一旦固化,形成的合金在随后的叠片中保持固体。 结果,制造复合的,多层的高性能电路板,通过固体合金在选定的焊盘处电连接。
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公开(公告)号:US5280414A
公开(公告)日:1994-01-18
申请号:US536145
申请日:1990-06-11
IPC分类号: H01R43/02 , B23K35/00 , B23K35/30 , H01R4/02 , H05K3/28 , H05K3/32 , H05K3/40 , H05K3/46 , H05K3/36 , B32B31/00 , H05K1/11
CPC分类号: B23K35/3013 , B23K35/001 , H01R4/02 , H05K3/4614 , H01L2924/0132 , H05K2201/0305 , H05K3/28 , H05K3/328 , H05K3/4038 , Y10S428/901 , Y10T156/1056 , Y10T29/49126
摘要: A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au-Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, multilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.
摘要翻译: 公开了一种同时层压电路化电介质层以形成多层高性能电路板并制造层间电连接的方法。 该方法选择将在一个低温下形成共晶体的两种元素,并且将固化形成合金,该合金将仅在任何后续层压所需的第二温度下再熔化。 使用瞬态液体粘合技术和足够的Au和Sn制成接头,以在低温下产生Au-Sn20wt%共晶。 一旦固化,形成的合金在随后的叠片中保持固体。 结果,制造复合多层高性能电路板,通过固体合金在选定的焊盘处电连接。
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公开(公告)号:US20100041226A1
公开(公告)日:2010-02-18
申请号:US12193644
申请日:2008-08-18
申请人: Jonathan D. Reid , Katie Qun Wang , Mark J. Willey
发明人: Jonathan D. Reid , Katie Qun Wang , Mark J. Willey
IPC分类号: H01L21/445 , C25D3/38 , C25D17/00
CPC分类号: H01L25/50 , C25D3/38 , C25D7/123 , C25D17/001 , C25D21/12 , H01L21/2885 , H01L21/76898 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. Low copper concentration and high acidity electroplating solution is used for deposition copper into the through silicon vias.
摘要翻译: 公开了一种半导体电镀工艺将铜沉积到通孔硅通孔中以完全填充通孔硅通孔。 直通硅通孔的直径可以大于约3微米,而深度大约为20微米。 低铜浓度和高酸性电镀溶液用于将铜沉积到通孔硅通孔中。
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公开(公告)号:US07622024B1
公开(公告)日:2009-11-24
申请号:US11040359
申请日:2005-01-20
申请人: Steven T. Mayer , Jonathan D. Reid
发明人: Steven T. Mayer , Jonathan D. Reid
CPC分类号: C25D17/12 , C25D7/123 , C25D17/001 , C25D17/008 , H01L21/2885 , Y10S204/07
摘要: A substantially uniform layer of a metal is electroplated onto a work piece having a seed layer thereon. This is accomplished by employing a “high resistance ionic current source,” which solves the terminal problem by placing a highly resistive membrane (e.g., a microporous ceramic or fretted glass element) in close proximity to the wafer, thereby swamping the system's resistance. The membrane thereby approximates a constant current source. By keeping the wafer close to the membrane surface, the ionic resistance from the top of the membrane to the surface is much less than the ionic path resistance to the wafer edge, substantially compensating for the sheet resistance in the thin metal film and directing additional current over the center and middle of the wafer.
摘要翻译: 将基本上均匀的金属层电镀在其上具有种子层的工件上。 这是通过使用“高电阻离子电流源”来实现的,其通过将高电阻膜(例如,微孔陶瓷或微波玻璃元件)放置在靠近晶片来解决端子问题,从而使系统的电阻变化。 因此,膜近似于恒定电流源。 通过保持晶片靠近膜表面,从膜顶部到表面的离子电阻远小于对晶片边缘的离子路径电阻,基本上补偿薄金属膜中的薄层电阻并引导附加电流 在晶片的中心和中间。
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公开(公告)号:US07442267B1
公开(公告)日:2008-10-28
申请号:US10999838
申请日:2004-11-29
IPC分类号: C22F1/14
CPC分类号: C22F1/14 , C23C16/18 , C23C16/56 , H01L21/76862 , H01L21/76864 , H01L21/76873 , H01L21/76874
摘要: A ruthenium-containing thin film is formed. Typically, the ruthenium-containing thin film has a thickness in a range of about from 1 nm to 20 nm. The ruthenium-containing thin film is annealed in an oxygen-free atmosphere, for example, in N2 forming gas, at a temperature in a range of about from 100° C. to 500° C. for a total time duration of about from 10 seconds to 1000 seconds. Thereafter, copper or other metal is deposited by electroplating or electroless plating onto the annealed ruthenium-containing thin film. In some embodiments, the ruthenium-containing thin film is also treated by UV radiation.
摘要翻译: 形成含钌的薄膜。 通常,含钌薄膜的厚度在约1nm至20nm的范围内。 含钌的薄膜在无氧气氛中,例如在N 2 O 2形成气体中,在约100℃至500℃的温度范围内退火,以便 总时间约10秒至1000秒。 此后,通过电镀或化学镀将铜或其它金属沉积到退火的含钌薄膜上。 在一些实施方案中,含钌的薄膜也通过UV辐射处理。
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公开(公告)号:US07097410B1
公开(公告)日:2006-08-29
申请号:US10379858
申请日:2003-03-04
申请人: Jonathan D. Reid , Steven T. Mayer , Seshasayee Varadarajan , David C. Smith , Evan E. Patton , Dinesh S. Kalakkad , Gary Lind , Richard S. Hill
发明人: Jonathan D. Reid , Steven T. Mayer , Seshasayee Varadarajan , David C. Smith , Evan E. Patton , Dinesh S. Kalakkad , Gary Lind , Richard S. Hill
CPC分类号: H01L21/2885 , C25D17/001 , Y10S414/135 , Y10S414/136
摘要: The orientation of a wafer with respect to the surface of an electrolyte is controlled during an electroplating process. The wafer is delivered to an electrolyte bath along a trajectory normal to the surface of the electrolyte. Along this trajectory, the wafer is angled before entry into the electrolyte for angled immersion. A wafer can be plated in an angled orientation or not, depending on what is optimal for a given situation. Also, in some designs, the wafer's orientation can be adjusted actively during immersion or during electroplating, providing flexibility in various electroplating scenarios.
摘要翻译: 在电镀过程中控制晶片相对于电解质表面的取向。 将晶片沿着垂直于电解质表面的轨迹输送到电解质浴中。 沿着该轨迹,晶片在进入电解质之前是成角度的,用于倾斜的浸入。 根据给定情况下的最佳选择,晶圆可以以倾斜的方向进行电镀。 此外,在一些设计中,晶片的取向可以在浸入期间或在电镀期间被主动调节,从而在各种电镀场景中提供灵活性。
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8.
公开(公告)号:US06884335B2
公开(公告)日:2005-04-26
申请号:US10441607
申请日:2003-05-20
申请人: Eric G. Webb , Jonathan D. Reid , John H. Sukamto , Sesha Varadarajan , Margolita M. Pollack , Bryan L. Buckalew , Tariq Majid
发明人: Eric G. Webb , Jonathan D. Reid , John H. Sukamto , Sesha Varadarajan , Margolita M. Pollack , Bryan L. Buckalew , Tariq Majid
IPC分类号: C25D5/04 , C25D5/18 , C25D7/12 , H01L21/288
CPC分类号: C25D5/04 , C25D5/18 , C25D7/123 , C25D17/001 , H01L21/2885 , Y10S428/935 , Y10T428/12993
摘要: A negative bias is applied to an integrated circuit wafer immersed in an electrolytic plating solution to generate a DC current. After about ten percent to sixty percent of the final layer thickness has formed in a first plating time, biasing is interrupted during short pauses during a second plating time to generate substantially zero DC current. The pauses are from about 2 milliseconds to 5 seconds long, and typically about 10 milliseconds to 500 milliseconds. Generally, about 2 pauses to 100 pauses are used, and typically about 3 pauses to 15 pauses. Generally, the DC current density during the second plating time is greater than the DC current density during the initial plating time. Typically, the integrated circuit wafer is rotated during electroplating. Preferably, the wafer is rotated at a slower rotation rate during the second plating time than during the first plating time.
摘要翻译: 将负偏压施加到浸在电解电镀溶液中的集成电路晶片以产生DC电流。 在第一电镀时间中已经形成最终层厚度的约百分之十到百分之六十之后,在第二电镀时间期间的短暂停期间偏压中断,以产生基本为零的DC电流。 停顿时间为大约2毫秒到5秒,通常为大约10毫秒到500毫秒。 通常,使用约2次暂停至100次暂停,通常约3次暂停至15次停顿。 通常,第二电镀时间期间的直流电流密度大于初始电镀时间期间的直流电流密度。 通常,电镀期间集成电路晶片旋转。 优选地,在第二电镀时间期间,晶片以比第一电镀时间期间更慢的旋转速度旋转。
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公开(公告)号:US06821407B1
公开(公告)日:2004-11-23
申请号:US10231147
申请日:2002-08-27
申请人: Jonathan D. Reid , Timothy Mark Archer , Thomas Tan Vu , Seshasayee Varadarajan , Jon Henri , Steven T. Mayer , David Sauer , Anita Kang , Gerald Feldewerth
发明人: Jonathan D. Reid , Timothy Mark Archer , Thomas Tan Vu , Seshasayee Varadarajan , Jon Henri , Steven T. Mayer , David Sauer , Anita Kang , Gerald Feldewerth
IPC分类号: C25D338
CPC分类号: C25D21/12 , C25D17/002 , C25D17/12 , C25F7/00 , H05K3/241
摘要: An electroplating system includes (a) a phosphorized anode having an average grain size of at least about 50 micrometers and (b) plating apparatus that separates the anode from the cathode and prevents most particles generated at the anode from passing to the cathode. The separation may be accomplished by interposing a microporous chemical transport barrier between the anode and cathode. The relatively few particles that are generated at the large grain phosphorized copper anode are prevented from passing into the cathode (wafer) chamber area and thereby causing a defect in the part.
摘要翻译: 电镀系统包括(a)平均晶粒尺寸为至少约50微米的磷化阳极和(b)将阳极与阴极分离的电镀装置,并防止在阳极处产生的大多数颗粒通过阴极。 分离可以通过在阳极和阴极之间插入微孔化学传输阻挡层来实现。 在大晶粒磷化铜阳极处产生的相对较少的颗粒被阻止进入阴极(晶片)室区域,从而导致该部分的缺陷。
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10.
公开(公告)号:US06664122B1
公开(公告)日:2003-12-16
申请号:US09996425
申请日:2001-11-27
IPC分类号: H01L2166
CPC分类号: H01L21/76843 , C23C18/1617 , C23C18/1669 , C23C18/1675 , C23C18/1676 , C23C18/168 , C23C18/1692 , C23C18/40 , H01L21/288 , H01L21/76864 , H01L21/76868 , H01L21/76873 , H01L2221/1089 , Y10S977/89
摘要: Disclosed is a procedure for deposition of a thin and relatively continuous electroless copper film on the substrate of sub-micron integrated circuit features. The electroless copper film is deposited onto a previously deposited PVD copper film, which may be discontinuous. The continuous film formed by electroless deposition allows for sufficient filling of the sub-micron integrated circuit features by electrodeposition. The electroless bath employed to form the continuous electroless copper film may be composed of a reducing agent, a complexing agent, a source of copper ions, a pH adjuster, and optionally one or more surfactants and/or stabilizers. In one example, the reducing agent contains an aldehyde moiety.
摘要翻译: 公开了在亚微米集成电路特征的衬底上沉积薄而相对连续的无电铜膜的步骤。 将化学镀铜膜沉积在预先沉积的PVD铜膜上,其可以是不连续的。 通过无电沉积形成的连续膜允许通过电沉积充分填充亚微米集成电路特征。 用于形成连续化学镀铜膜的无电镀浴可以由还原剂,络合剂,铜离子源,pH调节剂和任选的一种或多种表面活性剂和/或稳定剂组成。 在一个实例中,还原剂含有醛部分。
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