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23 条记录 (耗时 0.019 秒)

    Method of reducing contact size by spacer filling
    2.
    发明授权
    Method of reducing contact size by spacer filling 失效
    通过间隔物填充减小接触尺寸的方法

    公开(公告)号：US06420104B1

    公开(公告)日：2002-07-16

    申请号：US09705941

    申请日：2000-11-03

    申请人： Bharath Rangarajan ,  Stephen Keetai Park ,  Guarionex Morales

    发明人： Bharath Rangarajan ,  Stephen Keetai Park ,  Guarionex Morales

    IPC分类号： H01L214763

    CPC分类号： H01L21/76831 ,  H01L21/76816 ,  H01L21/76832

    摘要： A method of reducing contact size in an integrated circuit includes providing an insulating layer over a semiconductor substrate including a plurality of gate structures, creating an aperture extending through the insulating layer and having side walls, providing a spacer on the side walls of the aperture, and providing a contact in the aperture. The lateral sides of the contact abut the spacer. A contact structure is also disclosed in which a spacer separates a contact from a gate structure to avoid charge gain or loss between the contact and gate structure.

    摘要翻译： 减小集成电路中的接触尺寸的方法包括在包括多个栅极结构的半导体衬底之上提供绝缘层，形成延伸穿过绝缘层并具有侧壁的孔，在孔的侧壁上提供间隔物， 并在孔中提供接触。 接触件的侧面靠垫片。 还公开了一种接触结构，其中隔离物将接触与栅极结构分离以避免接触和栅极结构之间的电荷增益或损耗。

    Method of degassing low k dielectric for metal deposition
    4.
    发明授权
    Method of degassing low k dielectric for metal deposition 失效
    用于金属沉积的低k电介质的脱气方法

    公开(公告)号：US06436850B1

    公开(公告)日：2002-08-20

    申请号：US09652132

    申请日：2000-08-31

    申请人： Guarionex Morales

    发明人： Guarionex Morales

    IPC分类号： H01L214763

    CPC分类号： H01L21/76828 ,  H01L21/3124

    摘要： Multi-metallization level semiconductor devices are formed without degrading a low k dielectric gap fill material due to multiple pre-metallization degassing/outgassing heat treatments. Degradation of the low k material is substantially reduced or eliminated by employing time intervals for heat treatment which are not longer than the longest metal deposition step and temperatures below that which the dielectric material decomposes.

    摘要翻译： 由于多次预金属化除气/除气热处理，多金属化水平半导体器件形成而不降低低k电介质间隙填充材料。 通过采用不长于最长金属沉积步骤和低于电介质材料分解温度的温度的热处理时间间隔，可以显着降低或消除低k材料的劣化。

    Tungsten plug formation
    5.
    发明授权
    Tungsten plug formation 失效
    钨塞形成

    公开(公告)号：US06235632B1

    公开(公告)日：2001-05-22

    申请号：US09006495

    申请日：1998-01-13

    申请人： Takeshi Nogami ,  Guarionex Morales ,  Minh Van Ngo

    发明人： Takeshi Nogami ,  Guarionex Morales ,  Minh Van Ngo

    IPC分类号： H01L2144

    CPC分类号： H01L21/76864 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76895

    摘要： In a preferred embodiment, there is disclosed a method of forming a tungsten plug at the via level. A metal line is formed in a top portion of a first insulating layer. A second insulating layer is formed on the first insulating layer and over an exposed surface of the metal line. An etching process is applied to a region of the second insulating layer formed over the exposed surface of the metal line to create a contact hole within the region. The metal line is exposed at the region. A tungsten nitride thin film is deposited over the second insulating layer and the exposed metal line. A blanket tungsten thin film is deposited to fill the contact hole and to form a planar layer successively to the depositing of the tungsten nitride thin film. The tungsten nitride thin film and the blanket tungsten thin film are chemically mechanically polished until the upper surface of the second insulating layer is exposed.

    摘要翻译： 在优选实施例中，公开了一种在通孔级形成钨丝塞的方法。 金属线形成在第一绝缘层的顶部。 在第一绝缘层上和金属线的暴露表面上形成第二绝缘层。 对形成在金属线的暴露表面上的第二绝缘层的区域施加蚀刻处理，以在该区域内形成接触孔。 金属线暴露在该地区。 在第二绝缘层和暴露的金属线上沉积氮化钨薄膜。 沉积覆盖的钨薄膜以填充接触孔并且连续地形成平坦层以沉积氮化钨薄膜。 化学机械抛光氮化钨薄膜和覆盖钨薄膜，直到第二绝缘层的上表面露出。

    Surface treatment of low-k SiOF to prevent metal interaction
    7.
    发明授权
    Surface treatment of low-k SiOF to prevent metal interaction 有权
    表面处理低k SiOF以防止金属相互作用

    公开(公告)号：US5994778A

    公开(公告)日：1999-11-30

    申请号：US157240

    申请日：1998-09-18

    申请人： Richard J. Huang ,  Guarionex Morales ,  Simon Chan

    发明人： Richard J. Huang ,  Guarionex Morales ,  Simon Chan

    IPC分类号： H01L21/316 ,  H01L23/532 ,  H01L23/522

    CPC分类号： H01L21/02131 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/31629 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S257/915

    摘要： A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

    摘要翻译： 一种在制造半导体产品的方法中使用低选择性SiOF的方法，包括以下步骤：获得SiOF层; 并从SiOF层的表面上消耗氟。 在优选的实施方案中，耗尽步骤包括用含有氢的等离子体处理SiOF层的表面的步骤。 进一步优选的是，处理过的表面被钝化。 本发明还包括一种半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF半导体层包括其一个边缘处的第一区域，该第一区域耗尽氟 到预定深度。

    Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces
    8.
    发明授权
    Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces 有权
    集成电路，具有改善导电和电介质表面界面之间的粘附性

    公开(公告)号：US06281584B1

    公开(公告)日：2001-08-28

    申请号：US09373482

    申请日：1999-08-12

    申请人： Minh Van Ngo ,  Richard J. Huang ,  Guarionex Morales

    发明人： Minh Van Ngo ,  Richard J. Huang ,  Guarionex Morales

    IPC分类号： H01L2348

    CPC分类号： H01L21/31629 ,  H01L21/76801 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

    摘要翻译： 一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。 在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。 进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。 本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中SiOF电介质层包括其一个边缘处的第一区域，该第一区域耗尽氟 到预定深度。

    Method of silicide film formation onto a semiconductor substrate
    9.
    发明授权
    Method of silicide film formation onto a semiconductor substrate 失效
    在半导体衬底上形成硅化物膜的方法

    公开(公告)号：US06177345B1

    公开(公告)日：2001-01-23

    申请号：US09080405

    申请日：1998-05-18

    申请人： Guarionex Morales ,  Jianshi Wang ,  Judith Q. Rizzuto ,  Hao Fang

    发明人： Guarionex Morales ,  Jianshi Wang ,  Judith Q. Rizzuto ,  Hao Fang

    IPC分类号： H01L2144

    CPC分类号： H01L21/28518 ,  H01L21/32053

    摘要： A method of depositing metal silicide onto a semiconductor substrate includes a step of depositing, by a CVD process, a first metal silicide layer with silane gas onto the semiconductor substrate. The method also includes a step of thermally treating and chemically cleaning the semiconductor substrate. The method further includes a step of depositing, by the CVD process, a second metal silicide layer with silane gas onto the semiconductor substrate. By this method, cracks in the metal silicide formed on the semiconductor substrate are minimized.

    摘要翻译： 将金属硅化物沉积到半导体衬底上的方法包括通过CVD工艺将具有硅烷气体的第一金属硅化物层沉积到半导体衬底上的步骤。 该方法还包括对半导体衬底进行热处理和化学清洗的步骤。 该方法还包括通过CVD工艺将具有硅烷气体的第二金属硅化物层沉积到半导体衬底上的步骤。 通过这种方法，在半导体衬底上形成的金属硅化物中的裂纹被最小化。