公开(公告)号：US6084271A

公开(公告)日：2000-07-04

申请号：US187892

申请日：1998-11-06

申请人： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

发明人： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119 ,  H01L31/62

CPC分类号： H01L29/6659 ,  H01L29/0649 ,  H01L29/78

摘要： A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

公开(公告)号：US06670260B1

公开(公告)日：2003-12-30

申请号：US09577332

申请日：2000-05-24

申请人： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

发明人： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC分类号： H01L21425

CPC分类号： H01L29/6659 ,  H01L29/0649 ,  H01L29/78

摘要： A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

摘要翻译： 薄膜完全耗尽的绝缘体上硅（SOI）金属氧化物半导体场缺陷晶体管（MOSFET）利用局部绝缘结构。 局部绝缘结构包括沟道区下方的埋置二氧化硅区域。 MOSFET体的厚度非常小，而在沟道区域和掩埋的二氧化硅区域之外可用的硅可用于源极和漏极区域中足够的硅化物深度。 掩埋的二氧化硅区域可以通过沟槽隔离技术或LOCOS技术形成。

公开(公告)号：US06380019B1

公开(公告)日：2002-04-30

申请号：US09187498

申请日：1998-11-06

申请人： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

发明人： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC分类号： H01L2976

CPC分类号： H01L21/74 ,  H01L29/0649 ,  H01L29/6659

摘要： A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

摘要翻译： 薄膜完全耗尽的绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）利用局部绝缘结构。 局部绝缘结构包括沟道区下方的埋置二氧化硅区域。 MOSFET体的厚度非常小，而在沟道区域和掩埋的二氧化硅区域之外可用的硅可用于源极和漏极区域中足够的硅化物深度。 掩埋的二氧化硅区域可以通过沟槽隔离技术或LOCOS技术形成。

公开(公告)号：US06169039A

公开(公告)日：2001-01-02

申请号：US09187169

申请日：1998-11-06

申请人： Ming-Ren Lin ,  Shekhar Pramanick ,  David Bang

发明人： Ming-Ren Lin ,  Shekhar Pramanick ,  David Bang

IPC分类号： H01L2131

CPC分类号： H01L21/02118 ,  H01L21/02126 ,  H01L21/02134 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02351 ,  H01L21/31058 ,  H01L21/312 ,  H01L21/3124 ,  Y02P80/30

摘要： An integrated circuit and a method of forming an integrated circuit is described. The integrated circuit includes a silicon substrate, a dielectric stack formed on the silicon substrate, and conductive metal lines overlying the silicon substrate. A first layer of low-k dielectric material overlies the at least one conductive metal line, and a second layer of low-k dielectric material overlies the first layer of low-k dielectric material. The first layer of low-k dielectric material is electron beam (E-beam) cured and the second layer of low-k dielectric material is thermally cured.

摘要翻译： 描述集成电路和形成集成电路的方法。 集成电路包括硅衬底，形成在硅衬底上的电介质叠层和覆盖硅衬底的导电金属线。 低k电介质材料的第一层覆盖在至少一个导电金属线上，第二低k电介质材料层覆盖在第一低电介质材料层上。 第一层低k电介质材料是电子束（电子束）固化，第二层低k介电材料被热固化。

公开(公告)号：US6165902A

公开(公告)日：2000-12-26

申请号：US187520

申请日：1998-11-06

申请人： Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

发明人： Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

IPC分类号： H01L21/285 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28568

摘要： Low resistance contacts are formed on source/drain regions and gate electrodes by selectively depositing a reaction barrier layer and selectively depositing a metal layer on the reaction barrier layer. Embodiments include selectively depositing an alloy of cobalt and tungsten which functions as a reaction barrier layer preventing silicidation of a layer of nickel or cobalt selectively deposited thereon. Embodiments also include tailoring the composition of the cobalt tungsten alloy so that a thin silicide layer is formed thereunder for reduced contact resistance.

摘要翻译： 通过选择性地沉积反应阻挡层并在反应阻挡层上选择性地沉积金属层，在源/漏区和栅电极上形成低电阻触点。 实施方案包括选择性沉积钴和钨的合金，其用作反应阻挡层，防止选择性沉积在其上的镍或钴层的硅化。 实施例还包括定制钴钨合金的组成，使得在其下形成薄的硅化物层以降低接触电阻。

公开(公告)号：US06239452B1

公开(公告)日：2001-05-29

申请号：US09320682

申请日：1999-05-27

申请人： Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

发明人： Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

IPC分类号： H01L2184

CPC分类号： H01L29/6659 ,  H01L21/28097 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/665

摘要： A deep submicron MOS device having a self-aligned silicide gate structure and a method for forming the same is provided so as to overcome the problems of poly-Si depletion and boron penetration. A first Nickel silicide layer is formed between a gate oxide and a polycrystalline silicon gate electrode. Further, second Nickel silicide layers are formed over highly-doped source/drain regions. In this fashion, the reliability of the MOS device will be enhanced.

摘要翻译： 提供了具有自对准硅化物栅极结构的深亚微米MOS器件及其形成方法，以克服多Si耗尽和硼渗透的问题。 在栅极氧化物和多晶硅栅电极之间形成第一镍硅化物层。 此外，第二镍硅化物层形成在高掺杂源/漏区上。 以这种方式，MOS器件的可靠性将得到提高。

公开(公告)号：US06369429B1

公开(公告)日：2002-04-09

申请号：US09641727

申请日：2000-08-21

申请人： Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

发明人： Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

IPC分类号： H01L2352

CPC分类号： H01L21/28518 ,  H01L21/28568

摘要： Low resistance contacts are formed on source/drain regions and gate electrodes by selectively depositing a reaction barrier layer and selectively depositing a metal layer on the reaction barrier layer. Embodiments include selectively depositing an alloy of cobalt and tungsten which functions as a reaction barrier layer preventing silicidation of a layer of nickel or cobalt selectively deposited thereon. Embodiments also include tailoring the composition of the cobalt tungsten alloy so that a thin silicide layer is formed thereunder for reduced contact resistance.

摘要翻译： 通过选择性地沉积反应阻挡层并在反应阻挡层上选择性地沉积金属层，在源/漏区和栅电极上形成低电阻触点。 实施方案包括选择性沉积钴和钨的合金，其用作反应阻挡层，防止选择性沉积在其上的镍或钴层的硅化。 实施例还包括定制钴钨合金的组成，使得在其下形成薄的硅化物层以降低接触电阻。

公开(公告)号：US06180469B2

公开(公告)日：2001-01-30

申请号：US09187522

申请日：1998-11-06

申请人： Shekhar Pramanick ,  Qi Xiang ,  Ming-Ren Lin

发明人： Shekhar Pramanick ,  Qi Xiang ,  Ming-Ren Lin

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/3215 ,  H01L29/66515

摘要： Low resistivity contacts are formed on source/drain regions and gate electrodes at a suitable thickness to reduce parasitic series resistances, thereby significantly reducing consumption of underlying silicon, while significantly reducing junction leakage. Embodiments include selectively depositing a metal layer, such as nickel, on the source/drain regions and on the gate electrode and ion implanting to form a barrier layer within the nickel layers which does not react with silicon or nickel silicide during subsequent solicitation. The barrier layer confines salicidation to the relatively thin underlayer layer of nickel, thereby minimizing consumption of underlying silicon while the unsilicidized overlying nickel on the barrier layer ensures low sheet resistivity.

摘要翻译： 在源极/漏极区域和栅电极上以合适的厚度形成低电阻率接触以减少寄生串联电阻，从而显着降低底层硅的消耗，同时显着减少结漏电。 实施例包括在源极/漏极区域和栅极上选择性地沉积诸如镍的金属层和离子注入，以在镍层内形成阻挡层，其在随后的引诱期间不与硅或硅化镍反应。 阻挡层限制了相对薄的镍底层的盐析，从而最小化下层硅的消耗，而阻挡层上的无硅覆盖的镍确保了低的电阻率。

公开(公告)号：US5937315A

公开(公告)日：1999-08-10

申请号：US966288

申请日：1997-11-07

申请人： Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

发明人： Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49

CPC分类号： H01L29/6659 ,  H01L21/28097 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/665

摘要： A deep submicron MOS device having a self-aligned silicide gate structure and a method for forming the same is provided so as to overcome the problems of poly-Si depletion and boron penetration. A first Nickel silicide layer is formed between a gate oxide and a polycrystalline silicon gate electrode. Further, second Nickel silicide layers are formed over highly-doped source/drain regions. In this fashion, the reliability of the MOS device will be enhanced.

摘要翻译： 提供了具有自对准硅化物栅极结构的深亚微米MOS器件及其形成方法，以克服多Si耗尽和硼渗透的问题。 在栅极氧化物和多晶硅栅电极之间形成第一镍硅化物层。 此外，第二镍硅化物层形成在高掺杂源/漏区上。 以这种方式，MOS器件的可靠性将得到提高。

公开(公告)号：US20060177998A1

公开(公告)日：2006-08-10

申请号：US11379435

申请日：2006-04-20

申请人： Ming-Ren Lin ,  Witold Maszara ,  Haihong Wang ,  Bin Yu

发明人： Ming-Ren Lin ,  Witold Maszara ,  Haihong Wang ,  Bin Yu

IPC分类号： H01L21/3205

CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7842

摘要： A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.

摘要翻译： 一种方法可以包括在鳍结构上形成栅电极，在栅电极的顶表面上沉积第一金属层，执行第一硅化工艺以将栅电极的一部分转化为金属硅化物， 在金属硅化物化合物的顶表面上的金属层，并且执行第二硅化物处理以形成全硅化物栅电极。