公开(公告)号：US07163883B2

公开(公告)日：2007-01-16

申请号：US10694500

申请日：2003-10-27

申请人： Birendra N. Agarwala ,  Hormazdyar Minocher Dalal ,  Eric G. Liniger ,  Diana Llera-Hurlburt ,  Du Binh Nguyen ,  Richard W. Procter ,  Hazara Singh Rathore ,  Chunyan E. Tian ,  Brett H. Engel

发明人： Birendra N. Agarwala ,  Hormazdyar Minocher Dalal ,  Eric G. Liniger ,  Diana Llera-Hurlburt ,  Du Binh Nguyen ,  Richard W. Procter ,  Hazara Singh Rathore ,  Chunyan E. Tian ,  Brett H. Engel

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/8238

CPC分类号： H01L21/76831 ,  H01L21/76801 ,  H01L21/76807

摘要： An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.

摘要翻译： 围绕集成电路器件周边的边缘密封，其环境地保护铜电路免受在切割期间可能在低k层间电介质中形成的裂纹。 边缘密封件基本上构成在集成电路器件周边附近的铜电路和低k层间电介质之间的电介质壁。 电介质壁是与低k层间电介质不同的材料。

公开(公告)号：US06734090B2

公开(公告)日：2004-05-11

申请号：US10078861

申请日：2002-02-20

申请人： Birendra N. Agarwala ,  Hormazdyar Minocher Dalal ,  Eric G. Liniger ,  Diana Llera-Hurlburt ,  Du Binh Nguyen ,  Richard W. Procter ,  Hazara Singh Rathore ,  Chunyan E. Tian ,  Brett H. Engel

发明人： Birendra N. Agarwala ,  Hormazdyar Minocher Dalal ,  Eric G. Liniger ,  Diana Llera-Hurlburt ,  Du Binh Nguyen ,  Richard W. Procter ,  Hazara Singh Rathore ,  Chunyan E. Tian ,  Brett H. Engel

IPC分类号： H01L2144

CPC分类号： H01L21/76831 ,  H01L21/76801 ,  H01L21/76807

摘要： An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.

摘要翻译： 围绕集成电路器件周边的边缘密封，其环境地保护铜电路免受在切割期间可能在低k层间电介质中形成的裂纹。 边缘密封件基本上构成在集成电路器件周边附近的铜电路和低k层间电介质之间的电介质壁。 电介质壁是与低k层间电介质不同的材料。

公开(公告)号：US07279411B2

公开(公告)日：2007-10-09

申请号：US11164223

申请日：2005-11-15

申请人： Birendra N. Agarwala ,  Du Binh Nguyen ,  Hazara Singh Rathore

发明人： Birendra N. Agarwala ,  Du Binh Nguyen ,  Hazara Singh Rathore

IPC分类号： H01L21/4763

CPC分类号： H01L21/76847 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Device and method of fabricating device. The device includes a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line. The method includes forming a trench in a metal stripe of a dual damascene line, depositing a barrier layer in the trench, and filling a remainder of the trench with metal.

摘要翻译： 装置及其制造方法。 该装置包括具有金属线和通孔的双镶嵌线，以及布置成划分金属线的冗余衬垫。 该方法包括在双镶嵌线的金属条中形成沟槽，在沟槽中沉积阻挡层，并用金属填充沟槽的其余部分。

公开(公告)号：US07138714B2

公开(公告)日：2006-11-21

申请号：US10906265

申请日：2005-02-11

申请人： Du B. Nguyen ,  Birendra N. Agarwala ,  Conrad A Barile ,  Jawahar P. Nayak ,  Hazara S. Rathore

发明人： Du B. Nguyen ,  Birendra N. Agarwala ,  Conrad A Barile ,  Jawahar P. Nayak ,  Hazara S. Rathore

IPC分类号： H01L23/535

CPC分类号： H01L23/5283 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an interconnect structure that includes a diffusion barrier which is positioned within the structure in a fashion that increases the reliability and lifetime of the interconnect structure.

摘要翻译： 本发明提供一种互连结构，其包括以增加互连结构的可靠性和寿命的方式定位在结构内的扩散阻挡层。

公开(公告)号：US4970570A

公开(公告)日：1990-11-13

申请号：US423613

申请日：1989-10-16

申请人： Birendra N. Agarwala ,  Paul H. Palmateer ,  Da-Yuan Shih

发明人： Birendra N. Agarwala ,  Paul H. Palmateer ,  Da-Yuan Shih

IPC分类号： H01L21/48 ,  H01L23/498 ,  H05K3/34

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L2924/0002 ,  H05K3/3426

摘要： The present invention teaches a structure for reducing the stresses created on a substrate and on the bonding surface at which a connector is attached. The connector has a tapered or beveled head thereby tapering the stress away from the edges of the bonding surface and therefore away from the high stress areas of the substrate, preventing cracking and delamination problems that might otherwise result. The tapered-head geometry also allows greater flexibility in manufacturing the connectors particularly when fabricating pins using a cold-heading process in that a quarter shank diameter:pin head diameter ratio can be obtained.

摘要翻译： 本发明教导了一种用于减少在基板上以及在连接器所在的接合表面上产生的应力的结构。 连接器具有锥形或倾斜的头部，从而使应力使结合表面的边缘远离并且因此远离基板的高应力区域，从而防止否则可能导致的开裂和分层问题。 锥形头几何形状还允许制造连接器时的更大的灵活性，特别是当使用冷镦工艺制造销时，因为可以获得四分之一直径：销头直径比。

公开(公告)号：US07470613B2

公开(公告)日：2008-12-30

申请号：US11619748

申请日：2007-01-04

申请人： Birendra N. Agarwala ,  Eric M. Coker ,  Anthony Correale, Jr. ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Richard A. Wachnik

发明人： Birendra N. Agarwala ,  Eric M. Coker ,  Anthony Correale, Jr. ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Richard A. Wachnik

IPC分类号： H01L21/4763

CPC分类号： H01L21/76852 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure, the interconnect structure comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

摘要翻译： 一种用于形成互连结构的方法，所述互连结构包括：具有侧面和底部的下层导线，所述下层导线包括：下芯导体和下导电衬垫，所述下导电衬垫在侧面和底部 的下层电线; 具有侧面和底部的上部电线，所述上部电线包括上部芯导体和上部导电衬垫，所述上部导电衬垫位于所述上部电线的侧面和底部; 并且上导电衬套与下芯体导体接触并且还与衬套到衬垫接触区域中的下导电衬套接触。

公开(公告)号：US06271599B1

公开(公告)日：2001-08-07

申请号：US09366145

申请日：1999-08-03

申请人： Birendra N. Agarwala ,  William H. Ma

发明人： Birendra N. Agarwala ,  William H. Ma

IPC分类号： H01L2304

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

摘要： A wire interconnect structure for electrically and mechanically connecting an integrated circuit chip to a substrate and a process for manufacturing the same. The wire interconnect structure comprises an insulator layer disposed on an integrated circuit chip and an electrically conductive post extending through the insulator layer to the integrated circuit chip. The post has an elongated body, a bottom at one end of the body which is mechanically and electrically connected to the integrated circuit chip, and a top having a spherical shape at the opposite end of the body which extends outward from the insulator layer.

摘要翻译： 用于将集成电路芯片电气和机械连接到基板的导线互连结构及其制造方法。 导线互连结构包括设置在集成电路芯片上的绝缘体层和延伸穿过绝缘体层到集成电路芯片的导电柱。 该柱具有细长的主体，在主体的一端处的机械和电连接到集成电路芯片的底部，以及在主体的相对端处从绝缘体层向外延伸的具有球形的顶部。

公开(公告)号：US5251806A

公开(公告)日：1993-10-12

申请号：US870647

申请日：1992-04-16

申请人： Birendra N. Agarwala ,  Aziz M. Ahsan ,  Arthur Bross ,  Mark F. Chadurjian ,  Nicholas G. Koopman ,  Li-Chung Lee ,  Karl J. Puttlitz ,  Sudipta K. Ray ,  James G. Ryan ,  Joseph G. Schaefer ,  Kamalesh K. Srivastava ,  Paul A. Totta ,  Erick G. Walton ,  Adolf E. Wirsing

发明人： Birendra N. Agarwala ,  Aziz M. Ahsan ,  Arthur Bross ,  Mark F. Chadurjian ,  Nicholas G. Koopman ,  Li-Chung Lee ,  Karl J. Puttlitz ,  Sudipta K. Ray ,  James G. Ryan ,  Joseph G. Schaefer ,  Kamalesh K. Srivastava ,  Paul A. Totta ,  Erick G. Walton ,  Adolf E. Wirsing

IPC分类号： H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L21/283

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L2224/11901 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1367 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/13676 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L24/16 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15787 ,  H05K3/3431 ,  H05K3/3457

摘要： The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

摘要翻译： 本发明一般涉及新的互连及其制造方法，更具体地说，涉及一种细长的焊料互连及其制造方法。 在电子载体上，形成焊盘，在其上沉积焊料块并用金属层封盖，从而形成细长的焊料互连。 现在可以通过在已经被金属层覆盖的第一焊料块上形成第二焊料块来形成另外细长的焊料互连。 可以通过用金属覆盖层封盖前述焊料块和/或最后的焊料块来形成附加的细长焊料互连。 或者，封装层可以是形成在焊料块的侧壁上的侧壁间隔物的形式。

公开(公告)号：US5130779A

公开(公告)日：1992-07-14

申请号：US540256

申请日：1990-06-19

申请人： Birendra N. Agarwala ,  Aziz M. Ahsan ,  Arthur Bross ,  Mark F. Chadurjian ,  Nicholas G. Koopman ,  Li-Chung Lee ,  Karl J. Puttlitz ,  Sudipta K. Ray ,  James G. Ryan ,  Joseph G. Schaefer ,  Kamalesh K. Srivastava ,  Paul A. Totta ,  Erick G. Walton ,  Adolf E. Wirsing

发明人： Birendra N. Agarwala ,  Aziz M. Ahsan ,  Arthur Bross ,  Mark F. Chadurjian ,  Nicholas G. Koopman ,  Li-Chung Lee ,  Karl J. Puttlitz ,  Sudipta K. Ray ,  James G. Ryan ,  Joseph G. Schaefer ,  Kamalesh K. Srivastava ,  Paul A. Totta ,  Erick G. Walton ,  Adolf E. Wirsing

IPC分类号： H01L21/60 ,  H01L23/485 ,  H05K3/34

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1367 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/13676 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15787 ,  H05K3/3431 ,  H05K3/3457

摘要： The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

摘要翻译： 本发明一般涉及新的互连及其制造方法，更具体地说，涉及一种细长的焊料互连及其制造方法。 在电子载体上，形成焊盘，在其上沉积焊料块并用金属层封盖，从而形成细长的焊料互连。 现在可以通过在已经被金属层覆盖的第一焊料块上形成第二焊料块来形成另外细长的焊料互连。 可以通过用金属覆盖层封盖前述焊料块和/或最后的焊料块来形成附加的细长焊料互连。 或者，封装层可以是形成在焊料块的侧壁上的侧壁间隔物的形式。

公开(公告)号：US06825561B1

公开(公告)日：2004-11-30

申请号：US10250273

申请日：2003-06-19

申请人： Birendra N. Agarwala ,  Du B. Nguyen ,  Hazara S. Rathore

发明人： Birendra N. Agarwala ,  Du B. Nguyen ,  Hazara S. Rathore

IPC分类号： H01L2348

CPC分类号： H01L23/53295 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure for a semiconductor device includes a metallization line formed within a low-k dielectric material, the metallization line being surrounded on bottom and side surfaces thereof by a liner material. An embedded dielectric cap is formed over a top surface of the metallization line, wherein the embedded dielectric cap has a sufficient thickness so as to separate a top surface of the liner material from a hardmask layer formed over the low-k dielectric material.

摘要翻译： 用于半导体器件的互连结构包括形成在低k电介质材料内的金属化线，金属化线通过衬垫材料在其底表面和侧表面上包围。 嵌入的电介质盖形成在金属化线的顶表面上，其中嵌入的电介质盖具有足够的厚度，以便将衬垫材料的顶表面与形成在低k电介质材料上的硬掩模层分开。