公开(公告)号：US08753920B2

公开(公告)日：2014-06-17

申请号：US13195444

申请日：2011-08-01

申请人： Bo Sung Kim ,  Doo-Hyoung Lee ,  Yeon-Taek Jeong ,  Ki-Beom Lee ,  Young-Min Kim ,  Tae-Young Choi ,  Seon-Pil Jang ,  Kang-Moon Jo

发明人： Bo Sung Kim ,  Doo-Hyoung Lee ,  Yeon-Taek Jeong ,  Ki-Beom Lee ,  Young-Min Kim ,  Tae-Young Choi ,  Seon-Pil Jang ,  Kang-Moon Jo

IPC分类号： H01L21/36

CPC分类号： H01L21/02628 ,  H01L21/02554 ,  H01L21/02565

摘要： Provided is a precursor composition for an oxide semiconductor. The precursor composition for the oxide semiconductor includes a metal complex compound formed by a metal ion and an organic ligand, wherein the precursor composition is represented by the following Formula 1. MAn   (Formula 1) Herein, M is a metal ion, A is an organic ligand which includes α-substituted carboxylate, and n is a natural number.

摘要翻译： 提供一种用于氧化物半导体的前体组合物。 用于氧化物半导体的前体组合物包括由金属离子和有机配体形成的金属络合物，其中前体组合物由下式1表示。MAn（式1）这里，M是金属离子，A是 包括α-取代的羧酸酯的有机配体，n是自然数。

公开(公告)号：US20120244667A1

公开(公告)日：2012-09-27

申请号：US13195444

申请日：2011-08-01

申请人： Bo Sung KIM ,  Doo-Hyoung Lee ,  Yeon-Taek Jeong ,  Ki-Beom Lee ,  Young-Min Kim ,  Tae-Young Choi ,  Seon-Pil Jang ,  Kang-Moon Jo

发明人： Bo Sung KIM ,  Doo-Hyoung Lee ,  Yeon-Taek Jeong ,  Ki-Beom Lee ,  Young-Min Kim ,  Tae-Young Choi ,  Seon-Pil Jang ,  Kang-Moon Jo

IPC分类号： H01L21/335 ,  H01B1/12 ,  H01L21/20 ,  C07F17/00

CPC分类号： H01L21/02628 ,  H01L21/02554 ,  H01L21/02565

摘要： Provided is a precursor composition for an oxide semiconductor. The precursor composition for the oxide semiconductor includes a metal complex compound formed by a metal ion and an organic ligand, wherein the precursor composition is represented by the following Formula 1. MAn   (Formula 1( Herein, M is a metal ion, A is an organic ligand which includes α-substituted carboxylate, and n is a natural number.

摘要翻译： 提供一种用于氧化物半导体的前体组合物。 用于氧化物半导体的前体组合物包括由金属离子和有机配体形成的金属络合物，其中前体组合物由下式1表示。MAn（式1（其中M是金属离子，A是 包括α-取代的羧酸酯的有机配体，n是自然数。

公开(公告)号：US08760596B2

公开(公告)日：2014-06-24

申请号：US13173457

申请日：2011-06-30

申请人： Tae-Young Choi ,  Bo Sung Kim ,  Young Min Kim ,  Seon-Pil Jang ,  Kang Moon Jo ,  Yeon Taek Jeong ,  Ki Beom Lee

发明人： Tae-Young Choi ,  Bo Sung Kim ,  Young Min Kim ,  Seon-Pil Jang ,  Kang Moon Jo ,  Yeon Taek Jeong ,  Ki Beom Lee

IPC分类号： G02F1/136

CPC分类号： H01L27/1225 ,  G02F1/13439 ,  G02F2001/13685 ,  G02F2001/1676

摘要： A thin film transistor array panel includes a source electrode and a drain electrode on an insulating substrate, an oxide semiconductor on the insulating substrate and overlapping the source electrode and the drain electrode, a passivation layer overlapping the oxide semiconductor and on the insulating substrate, a gate electrode on the passivation layer, and a pixel electrode connected to the drain electrode. The gate electrode and the pixel electrode include a same material. The oxide semiconductor is between the source electrode and the gate electrode, and between the drain electrode and the gate electrode in a cross-sectional view of the thin film transistor array panel.

摘要翻译： 薄膜晶体管阵列面板包括绝缘基板上的源极和漏电极，绝缘基板上的氧化物半导体，与源电极和漏电极重叠，钝化层与氧化物半导体和绝缘基板上重叠， 钝化层上的栅极电极和连接到漏电极的像素电极。 栅电极和像素电极包括相同的材料。 在薄膜晶体管阵列面板的截面图中，氧化物半导体位于源电极和栅电极之间，在漏电极和栅电极之间。

公开(公告)号：US20110140094A1

公开(公告)日：2011-06-16

申请号：US12823043

申请日：2010-06-24

申请人： Tae-Young Choi ,  Hi-Kuk Lee ,  Bo-Sung Kim ,  Young-Min Kim ,  Seung-Hwan Cho ,  Young-Soo Yoon ,  Yeon-Taek Jeong ,  Seon-Pil Jang

发明人： Tae-Young Choi ,  Hi-Kuk Lee ,  Bo-Sung Kim ,  Young-Min Kim ,  Seung-Hwan Cho ,  Young-Soo Yoon ,  Yeon-Taek Jeong ,  Seon-Pil Jang

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/34 ,  H01L29/12

CPC分类号： H01L29/66765 ,  H01L21/02554 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/7869

摘要： A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; an etching stop layer disposed on the semiconductor; an insulating layer disposed on the gate insulating layer; and a source electrode and a drain electrode overlapping the semiconductor. The semiconductor and the gate insulating layer have a first portion on which the etching stop layer and the insulating layer are disposed, and a second portion on which etching stop layer and the insulating layer are not disposed. The source electrode and the drain electrode are disposed on the second portion of the semiconductor and the gate insulating layer

摘要翻译： 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：栅极，设置在绝缘基板上; 设置在栅电极上的栅极绝缘层; 设置在所述栅极绝缘层上的半导体; 设置在所述半导体上的蚀刻停止层; 设置在所述栅极绝缘层上的绝缘层; 以及与半导体重叠的源电极和漏电极。 半导体和栅极绝缘层具有其上设置有蚀刻停止层和绝缘层的第一部分，以及不设置蚀刻停止层和绝缘层的第二部分。 源电极和漏极设置在半导体的第二部分和栅极绝缘层上

公开(公告)号：US20100308326A1

公开(公告)日：2010-12-09

申请号：US12790188

申请日：2010-05-28

申请人： Young-Min KIM ,  Bo-Sung Kim ,  Yeon-Taek Jeong ,  Tae-Young Choi ,  Seon-Pil Jang ,  Seung-Hwan Cho ,  Bo-Kyoung Ahn ,  Byeong-Soo Bae ,  Seok-Jun Seo

发明人： Young-Min KIM ,  Bo-Sung Kim ,  Yeon-Taek Jeong ,  Tae-Young Choi ,  Seon-Pil Jang ,  Seung-Hwan Cho ,  Bo-Kyoung Ahn ,  Byeong-Soo Bae ,  Seok-Jun Seo

IPC分类号： H01L29/786 ,  H01L21/34

CPC分类号： H01L27/1225 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02628 ,  H01L29/7869

摘要： A thin-film transistor array panel includes: an insulating substrate; an oxide semiconductor layer that is formed on the insulating substrate and includes a metal inorganic salt and zinc acetate; a gate electrode overlapping with the oxide semiconductor layer; a gate insulating film that is interposed between the oxide semiconductor layer and the gate electrode; and a source electrode and a drain electrode that at least partially overlap the oxide semiconductor layer and are separated from each other.

摘要翻译： 薄膜晶体管阵列面板包括：绝缘基板; 形成在所述绝缘基板上并且包括金属无机盐和乙酸锌的氧化物半导体层; 栅电极与氧化物半导体层重叠; 介于氧化物半导体层和栅电极之间的栅极绝缘膜; 以及与氧化物半导体层至少部分重叠并且彼此分离的源电极和漏电极。

公开(公告)号：US08519393B2

公开(公告)日：2013-08-27

申请号：US12823043

申请日：2010-06-24

申请人： Tae-Young Choi ,  Hi-Kuk Lee ,  Bo-Sung Kim ,  Young-Min Kim ,  Seung-Hwan Cho ,  Young-Soo Yoon ,  Yeon-Taek Jeong ,  Seon-Pil Jang

发明人： Tae-Young Choi ,  Hi-Kuk Lee ,  Bo-Sung Kim ,  Young-Min Kim ,  Seung-Hwan Cho ,  Young-Soo Yoon ,  Yeon-Taek Jeong ,  Seon-Pil Jang

IPC分类号： H01L27/146 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L21/02554 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/7869

摘要： A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; an etching stop layer disposed on the semiconductor; an insulating layer disposed on the gate insulating layer; and a source electrode and a drain electrode overlapping the semiconductor. The semiconductor and the gate insulating layer have a first portion on which the etching stop layer and the insulating layer are disposed, and a second portion on which etching stop layer and the insulating layer are not disposed. The source electrode and the drain electrode are disposed on the second portion of the semiconductor and the gate insulating layer.

摘要翻译： 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：栅极，设置在绝缘基板上; 设置在栅电极上的栅极绝缘层; 设置在所述栅极绝缘层上的半导体; 设置在所述半导体上的蚀刻停止层; 设置在所述栅极绝缘层上的绝缘层; 以及与半导体重叠的源电极和漏电极。 半导体和栅极绝缘层具有其上设置有蚀刻停止层和绝缘层的第一部分，以及不设置蚀刻停止层和绝缘层的第二部分。 源电极和漏极设置在半导体的第二部分和栅极绝缘层上。

公开(公告)号：US20130056828A1

公开(公告)日：2013-03-07

申请号：US13436689

申请日：2012-03-30

申请人： Yeon Taek JEONG ,  Bo Sung Kim ,  Doo-Hyoung Lee ,  June Whan Choi ,  Tae-Young Choi ,  Kano Masataka

发明人： Yeon Taek JEONG ,  Bo Sung Kim ,  Doo-Hyoung Lee ,  June Whan Choi ,  Tae-Young Choi ,  Kano Masataka

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/42384 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/512 ,  H01L29/786 ,  H01L2029/42388

摘要： A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a semiconductor layer disposed on the substrate and including at least a portion overlapping the gate electrode; a gate insulating layer disposed between the gate line and the semiconductor layer; and a source electrode and a drain electrode disposed on the substrate and facing each other over a channel region of the semiconductor layer. The gate insulating layer includes a first region and a second region, the first region corresponds to the channel region of the semiconductor layer, the first region is made of a first material, the second region is made of a second material, and the first material and the second material have different atomic number ratios of carbon and silicon.

公开(公告)号：US08871577B2

公开(公告)日：2014-10-28

申请号：US13436689

申请日：2012-03-30

申请人： Yeon Taek Jeong ,  Bo Sung Kim ,  Doo-Hyoung Lee ,  June Whan Choi ,  Tae-Young Choi ,  Kano Masataka

发明人： Yeon Taek Jeong ,  Bo Sung Kim ,  Doo-Hyoung Lee ,  June Whan Choi ,  Tae-Young Choi ,  Kano Masataka

IPC分类号： H01L21/00 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/42384 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/512 ,  H01L29/786 ,  H01L2029/42388

摘要： A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a semiconductor layer disposed on the substrate and including at least a portion overlapping the gate electrode; a gate insulating layer disposed between the gate line and the semiconductor layer; and a source electrode and a drain electrode disposed on the substrate and facing each other over a channel region of the semiconductor layer. The gate insulating layer includes a first region and a second region, the first region corresponds to the channel region of the semiconductor layer, the first region is made of a first material, the second region is made of a second material, and the first material and the second material have different atomic number ratios of carbon and silicon.

摘要翻译： 提供薄膜晶体管。 根据本发明的示例性实施例的薄膜晶体管包括：基板; 栅极线，设置在所述基板上并且包括栅电极; 半导体层，设置在所述基板上，并且至少包括与所述栅电极重叠的部分; 设置在所述栅极线和所述半导体层之间的栅极绝缘层; 以及设置在所述基板上并且在所述半导体层的沟道区域上彼此面对的源电极和漏电极。 栅极绝缘层包括第一区域和第二区域，第一区域对应于半导体层的沟道区域，第一区域由第一材料制成，第二区域由第二材料制成，第一材料 并且第二材料具有不同的碳和硅原子数比。

公开(公告)号：US08877551B2

公开(公告)日：2014-11-04

申请号：US13619075

申请日：2012-09-14

申请人： Bo-Sung Kim ,  Jun-Ho Song ,  Doo-Na Kim ,  Kang-Moon Jo ,  Tae-Young Choi ,  Masataka Kano ,  Yeon-Taek Jeong

发明人： Bo-Sung Kim ,  Jun-Ho Song ,  Doo-Na Kim ,  Kang-Moon Jo ,  Tae-Young Choi ,  Masataka Kano ,  Yeon-Taek Jeong

IPC分类号： H01L21/00

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/66969

摘要： In a method of manufacturing a thin film transistor, a gate electrode is formed on a first surface of a base substrate, a oxide semiconductor layer, insulation layer and photo resist layer are formed an the fast surface of the base substrate having the gate electrode. The insulation layer and the oxide semiconductor layer are patterned using a first photo resist pattern to form an etch-stopper and an active pattern. A source and a drain electrode are formed on the base substrate having the active pattern and the etch-stopper, the source electrode and the drain electrode are overlapped with both ends of the etch-stopper and spaced apart from each other. Therefore, a manufacturing cost may be decreased by omitting a mask when forming the active pattern and the etch-stopper.

摘要翻译： 在制造薄膜晶体管的方法中，在具有栅电极的基底基板的快速表面上，在基底基板的第一表面，氧化物半导体层，绝缘层和光致抗蚀剂层上形成栅电极。 使用第一光致抗蚀剂图案对绝缘层和氧化物半导体层进行构图，以形成蚀刻停止层和活性图案。 源极和漏极形成在具有有源图案的基底基板上，并且蚀刻停止器，源极电极和漏电极与蚀刻停止器的两端重叠并且彼此间隔开。 因此，当形成活性图案和蚀刻停止物时，可以通过省略掩模来降低制造成本。

公开(公告)号：US08633498B2

公开(公告)日：2014-01-21

申请号：US13112381

申请日：2011-05-20

申请人： Tae-Young Choi ,  Kang-Moon Jo ,  Bo-Sung Kim ,  Young-Min Kim

发明人： Tae-Young Choi ,  Kang-Moon Jo ,  Bo-Sung Kim ,  Young-Min Kim

IPC分类号： H01L29/18

CPC分类号： H01L27/1288 ,  H01L27/1225 ,  H01L27/1292

摘要： A display substrate includes a base substrate, a data line, a gate line, a switching element, a self assembled monolayer (SAM) and a pixel electrode. The data line is formed on the base substrate. The gate line is formed across the data line. The switching element includes a source electrode electrically connected to the data line, a drain electrode spaced apart from the source electrode, a semiconductor pattern covering the source and drain electrodes, and a gate electrode electrically connected to the gate line and facing the semiconductor pattern. The SAM is disposed around the semiconductor pattern and a conductive pattern including the data line. The pixel electrode is electrically connected to the switching element.

摘要翻译： 显示基板包括基底基板，数据线，栅极线，开关元件，自组装单层（SAM）和像素电极。 数据线形成在基底基板上。 栅极线跨越数据线形成。 开关元件包括电连接到数据线的源电极，与源电极间隔开的漏电极，覆盖源电极和漏电极的半导体图案，以及电连接到栅极线并面向半导体图案的栅电极。 SAM围绕半导​​体图案设置，并且包括数据线的导电图案。 像素电极电连接到开关元件。