公开(公告)号：US20130050885A1

公开(公告)日：2013-02-28

申请号：US13217533

申请日：2011-08-25

申请人： Bo-Ting Chen ,  Tzu-Heng Chang

发明人： Bo-Ting Chen ,  Tzu-Heng Chang

IPC分类号： H02H9/04

CPC分类号： H02H9/04 ,  H02H9/046

摘要： Some embodiments relate to an electrostatic discharge (ESD) protection device to protect a circuit that is electrically connected to first and second circuit nodes from an ESD event. The ESD protection device includes a first electrical path extending between the first and second circuit nodes and including first and second ESD detection elements arranged thereon. The ESD protection device also includes first and second voltage bias elements having respective inputs electrically connected to respective outputs of the first and second ESD detection elements. A second electrical path extends between the first and second circuit nodes and is in parallel with the first electrical path. The second electrical path includes a voltage controlled shunt network having at least two control terminals electrically connected to respective outputs of the first and second voltage bias elements. Other embodiments are also disclosed.

摘要翻译： 一些实施例涉及用于保护电连接到第一和第二电路节点的电路与ESD事件的静电放电（ESD）保护装置。 ESD保护装置包括在第一和第二电路节点之间延伸并且包括布置在其上的第一和第二ESD检测元件的第一电路径。 ESD保护装置还包括具有电连接到第一和第二ESD检测元件的相应输出的相应输入的第一和第二电压偏置元件。 第二电路在第一和第二电路节点之间延伸并与第一电路平行。 第二电路包括电压控制并联网络，其具有电连接到第一和第二电压偏置元件的相应输出的至少两个控制端子。 还公开了其他实施例。

公开(公告)号：US08867183B2

公开(公告)日：2014-10-21

申请号：US13217533

申请日：2011-08-25

申请人： Bo-Ting Chen ,  Tzu-Heng Chang

发明人： Bo-Ting Chen ,  Tzu-Heng Chang

IPC分类号： H02H9/04

CPC分类号： H02H9/04 ,  H02H9/046

摘要： Some embodiments relate to an electrostatic discharge (ESD) protection device to protect a circuit that is electrically connected to first and second circuit nodes from an ESD event. The ESD protection device includes a first electrical path extending between the first and second circuit nodes and including first and second ESD detection elements arranged thereon. The ESD protection device also includes first and second voltage bias elements having respective inputs electrically connected to respective outputs of the first and second ESD detection elements. A second electrical path extends between the first and second circuit nodes and is in parallel with the first electrical path. The second electrical path includes a voltage controlled shunt network having at least two control terminals electrically connected to respective outputs of the first and second voltage bias elements. Other embodiments are also disclosed.

摘要翻译： 一些实施例涉及用于保护电连接到第一和第二电路节点的电路与ESD事件的静电放电（ESD）保护装置。 ESD保护装置包括在第一和第二电路节点之间延伸并且包括布置在其上的第一和第二ESD检测元件的第一电路径。 ESD保护装置还包括具有电连接到第一和第二ESD检测元件的相应输出的相应输入的第一和第二电压偏置元件。 第二电路在第一和第二电路节点之间延伸并与第一电路平行。 第二电路包括电压控制并联网络，其具有电连接到第一和第二电压偏置元件的相应输出的至少两个控制端子。 还公开了其他实施例。

公开(公告)号：US20090230400A1

公开(公告)日：2009-09-17

申请号：US12198081

申请日：2008-08-25

申请人： Chia-Wen Chang ,  Jiun-Jia Huang ,  Tzu-Heng Chang ,  Tan-Fu Lei ,  Szu-Fen Chen

发明人： Chia-Wen Chang ,  Jiun-Jia Huang ,  Tzu-Heng Chang ,  Tan-Fu Lei ,  Szu-Fen Chen

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/78696 ,  H01L29/66757 ,  H01L29/66787 ,  H01L29/785

摘要： A method for fabricating a thin film transistor is described. The method includes: providing a substrate; forming a sacrificial layer on the substrate; forming a polysilicon pattern layer on the substrate to surround the sacrificial layer; forming a gate insulation layer to cover at least the polysilicon pattern layer; forming a gate pattern on the gate insulation layer above the polysilicon pattern layer; forming a source region, a drain region, and an active region in the polysilicon pattern layer, wherein the active region is between the source region and the drain region; forming a passivation layer to cover the gate pattern and a portion of the gate insulation layer; forming a source conductive layer and a drain conductive layer on the passivation layer, wherein the source conductive layer and the drain conductive layer are electrically connected to the source region and the drain region of the polysilicon pattern layer respectively.

摘要翻译： 对薄膜晶体管的制造方法进行说明。 该方法包括：提供衬底; 在所述基板上形成牺牲层; 在所述衬底上形成多晶硅图案层以围绕所述牺牲层; 形成栅绝缘层以至少覆盖所述多晶硅图案层; 在多晶硅图案层上方的栅极绝缘层上形成栅极图案; 在所述多晶硅图案层中形成源极区，漏极区和有源区，其中所述有源区在所述源极区和所述漏极区之间; 形成钝化层以覆盖所述栅极图案和所述栅极绝缘层的一部分; 在所述钝化层上形成源极导电层和漏极导电层，其中所述源极导电层和所述漏极导电层分别电连接到所述多晶硅图案层的源极区域和所述漏极区域。

公开(公告)号：US20140027815A1

公开(公告)日：2014-01-30

申请号：US13558154

申请日：2012-07-25

申请人： Yu-Ti Su ,  Tzu-Heng Chang ,  Jen-Chou Tseng ,  Ming-Hsiang Song

发明人： Yu-Ti Su ,  Tzu-Heng Chang ,  Jen-Chou Tseng ,  Ming-Hsiang Song

IPC分类号： H01L27/06 ,  H01L21/8222

CPC分类号： H01L27/0817 ,  H01L27/0262 ,  H01L29/7436

摘要： Fast turn on silicon controlled rectifiers for ESD protection. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of a second conductivity type; a second well of the second conductivity type; a first diffused region of the first conductivity type and coupled to a first terminal; a first diffused region of the second conductivity type; a second diffused region of the first conductivity type; a second diffused region of the second conductivity type in the second well; wherein the first diffused region of the first conductivity type and the first diffused region of the second conductivity type form a first diode, and the second diffused region of the first conductivity type and the second diffused region of the second conductivity type form a second diode, and the first and second diodes are series coupled between the first terminal and the second terminal.

摘要翻译： 快速开启可控硅整流器，实现ESD保护。 半导体器件包括第一导电类型的半导体衬底; 第二导电类型的第一阱; 第二导电类型的第二阱; 第一导电类型的第一扩散区域并耦合到第一端子; 第二导电类型的第一扩散区域; 第一导电类型的第二扩散区域; 第二导电类型的第二扩散区域; 其中第一导电类型的第一扩散区域和第二导电类型的第一扩散区域形成第一二极管，并且第一导电类型的第二扩散区域和第二导电类型的第二扩散区域形成第二二极管， 并且第一和第二二极管串联耦合在第一端子和第二端子之间。

公开(公告)号：US20150109705A1

公开(公告)日：2015-04-23

申请号：US14147606

申请日：2014-01-06

申请人： Tzu-Heng Chang ,  Fu-Yi Tsai ,  Chia-Ku Tsai

发明人： Tzu-Heng Chang ,  Fu-Yi Tsai ,  Chia-Ku Tsai

IPC分类号： H01L27/02

CPC分类号： H01L27/0266 ,  H01L27/0251

摘要： A method for performing electrostatic discharge (ESD) protection and an associated apparatus are provided, where the method is applied to an electronic device, and the method includes: utilizing a trigger source formed with a plurality of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) to trigger a discharge operation, where the gate and the drain of any MOSFET within the plurality of MOSFETs are electrically connected to each other, causing the MOSFET to be utilized as a two-terminal component, and the MOSFETs that are respectively utilized as two-terminal components are connected in series; and utilizing an ESD apparatus to perform the discharge operation in response to the trigger of the trigger source, in order to perform ESD protection on the apparatus.

摘要翻译： 提供了一种用于执行静电放电（ESD）保护的方法和相关联的装置，其中该方法应用于电子设备，并且该方法包括：利用由多个金属氧化物半导体场效应晶体管（MOSFET）形成的触发源， 以触​​发放电操作，其中多个MOSFET内的任何MOSFET的栅极和漏极彼此电连接，导致MOSFET用作二端子部件，并且分别用作二端子MOSFET的MOSFET， 端子部件串联连接; 并且利用ESD装置响应于触发源的触发来执行放电操作，以便对该装置执行ESD保护。

公开(公告)号：US08759871B2

公开(公告)日：2014-06-24

申请号：US13176780

申请日：2011-07-06

申请人： Ming-Hsiang Song ,  Jam-Wem Lee ,  Tzu-Heng Chang ,  Yu-Ying Hsu

发明人： Ming-Hsiang Song ,  Jam-Wem Lee ,  Tzu-Heng Chang ,  Yu-Ying Hsu

IPC分类号： H01L29/66

CPC分类号： H01L27/0262

摘要： An ESD protection circuit includes a pad of an IC, circuitry coupled to the pad for buffering data, an RC power clamp on the IC, and first and second silicon controlled rectifier (SCR) circuits. The RC power clamp is coupled between a positive power supply terminal and a ground terminal. The first SCR circuit is coupled between the pad and the positive power supply terminal. The first SCR circuit has a first trigger input coupled to the RC power clamp circuit. The second SCR circuit is coupled between the pad and the ground terminal. The second SCR circuit has a second trigger input coupled to the RC power clamp circuit. At least one of the SCR circuits includes a gated diode configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal.

摘要翻译： ESD保护电路包括IC的焊盘，耦合到用于缓冲数据的焊盘的电路，IC上的RC功率钳，以及第一和第二可硅可控整流器（SCR）电路。 RC电源钳位在正电源端子和接地端子之间。 第一SCR电路耦合在焊盘和正电源端子之间。 第一SCR电路具有耦合到RC功率钳位电路的第一触发输入。 第二SCR电路耦合在焊盘和接地端子之间。 第二SCR电路具有耦合到RC功率钳位电路的第二触发输入。 SCR电路中的至少一个包括栅极二极管，其被配置为选择性地在焊盘与正电源端子和接地端子之一之间提供短路或相对导电的电路径。

公开(公告)号：US08692289B2

公开(公告)日：2014-04-08

申请号：US13558154

申请日：2012-07-25

申请人： Yu-Ti Su ,  Tzu-Heng Chang ,  Jen-Chou Tseng ,  Ming-Hsiang Song

发明人： Yu-Ti Su ,  Tzu-Heng Chang ,  Jen-Chou Tseng ,  Ming-Hsiang Song

IPC分类号： H01L29/74 ,  H01L31/111 ,  H02H3/00 ,  H02H7/00 ,  H02H9/02

CPC分类号： H01L27/0817 ,  H01L27/0262 ,  H01L29/7436

摘要： Fast turn on silicon controlled rectifiers for ESD protection. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of a second conductivity type; a second well of the second conductivity type; a first diffused region of the first conductivity type and coupled to a first terminal; a first diffused region of the second conductivity type; a second diffused region of the first conductivity type; a second diffused region of the second conductivity type in the second well; wherein the first diffused region of the first conductivity type and the first diffused region of the second conductivity type form a first diode, and the second diffused region of the first conductivity type and the second diffused region of the second conductivity type form a second diode, and the first and second diodes are series coupled between the first terminal and the second terminal.

摘要翻译： 快速开启可控硅整流器，实现ESD保护。 半导体器件包括第一导电类型的半导体衬底; 第二导电类型的第一阱; 第二导电类型的第二阱; 第一导电类型的第一扩散区域并耦合到第一端子; 第二导电类型的第一扩散区域; 第一导电类型的第二扩散区域; 第二导电类型的第二扩散区域; 其中第一导电类型的第一扩散区域和第二导电类型的第一扩散区域形成第一二极管，并且第一导电类型的第二扩散区域和第二导电类型的第二扩散区域形成第二二极管， 并且第一和第二二极管串联耦合在第一端子和第二端子之间。

公开(公告)号：US20120329203A1

公开(公告)日：2012-12-27

申请号：US13166352

申请日：2011-06-22

申请人： LIANG-TUNG CHANG ,  Tzu-Heng Chang

发明人： LIANG-TUNG CHANG ,  Tzu-Heng Chang

IPC分类号： H01L31/18 ,  H01L21/20

CPC分类号： H01L31/1804 ,  C30B11/00 ,  C30B11/001 ,  C30B15/04 ,  C30B15/08 ,  H01L31/068 ,  H01L31/075 ,  H01L31/182 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521

摘要： The present invention is to provide a method of creating a PIN silicon thin film comprising the steps of providing a molten P-type, Intrinsic and N-type semiconductor material. Next, it is performing a down draw process or a casting process of the molten P-type. Intrinsic and N-type semiconductor material. Then, it is selectively performing a dual-side rolling process to create a P-type, Intrinsic and N-type semiconductor ribbon. Subsequently, it is performing a step of joining the P-type, Intrinsic and N-type semiconductor ribbon to form a PIN semiconductor ribbon. Finally, it is performing a roll press process or a pressing process to the PIN semiconductor ribbon to create the PIN semiconductor thin film.

摘要翻译： 本发明提供一种制造PIN硅薄膜的方法，其包括提供熔融P型，本征型和N型半导体材料的步骤。 接下来，正在进行熔融P型的下拉工序或铸造工序。 本征和N型半导体材料。 然后，选择性地执行双面轧制工艺以产生P型，本征和N型半导体带。 随后，正在执行连接P型，本征和N型半导体带以形成PIN半导体带的步骤。 最后，对PIN半导体薄带进行辊压加工或压制加工以产生PIN半导体薄膜。

公开(公告)号：US08963200B2

公开(公告)日：2015-02-24

申请号：US13527833

申请日：2012-06-20

申请人： Jam-Wem Lee ,  Tzu-Heng Chang ,  Tsung-Che Tsai ,  Ming-Hsiang Song

发明人： Jam-Wem Lee ,  Tzu-Heng Chang ,  Tsung-Che Tsai ,  Ming-Hsiang Song

IPC分类号： H01L29/45

CPC分类号： H01L27/0262 ,  H01L21/8248 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0921 ,  H01L29/0619 ,  H01L29/73 ,  H01L29/812

摘要： Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.

摘要翻译： 提高保持电压SCR的方法和装置。 半导体器件包括第一导电类型的半导体衬底; 第一导电类型的第一井; 与第一阱相邻的第二导电类型的第二阱，形成p-n结的第一阱和第二阱的交点; 第一导电类型的第一扩散区域形成在第一阱处并且耦合到接地端子; 形成在第一阱处的第二导电类型的第一扩散区域; 第二导电类型的第二扩散区域形成在第二阱处并耦合到焊盘端子; 第二导电类型的第二扩散区形成在第二阱中; 以及与第二导电类型的第一扩散区相邻形成的与肖特基结相连的接地端子。 公开了用于形成装置的方法。

公开(公告)号：US08730626B2

公开(公告)日：2014-05-20

申请号：US13252396

申请日：2011-10-04

申请人： Jen-Chou Tseng ,  Tzu-Heng Chang ,  Ming-Hsiang Song

发明人： Jen-Chou Tseng ,  Tzu-Heng Chang ,  Ming-Hsiang Song

IPC分类号： H02H9/00

CPC分类号： H01L27/0292 ,  H01L21/822 ,  H01L23/481 ,  H01L23/60 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0266 ,  H01L27/0285 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip includes a first circuit, a second circuit, a first interconnect, and a least one protection circuit. The first circuit has a first node, a first operational voltage node, and a first reference voltage node. The second circuit has a second node, a second operational voltage node, and a second reference voltage node. The first interconnect is configured to electrically connect the first node and the second node to form a 2.5D or a 3D integrated circuit. The at least one protection circuit is located at one or various locations of the chip.

摘要翻译： 芯片包括第一电路，第二电路，第一互连和至少一个保护电路。 第一电路具有第一节点，第一工作电压节点和第一参考电压节点。 第二电路具有第二节点，第二工作电压节点和第二参考电压节点。 第一互连被配置为电连接第一节点和第二节点以形成2.5D或3D集成电路。 至少一个保护电路位于芯片的一个或多个位置。