公开(公告)号：US06525417B2

公开(公告)日：2003-02-25

申请号：US10124211

申请日：2002-04-16

申请人： Bong-seok Chae ,  Kye-hyun Kyung

发明人： Bong-seok Chae ,  Kye-hyun Kyung

IPC分类号： H01L2348

CPC分类号： H01L23/5222 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： A step height between first and second elevated conductive lines that are laterally spaced apart on an integrated circuit substrate may be reduced by forming a dummy conductive line beneath the second conductive line, to further elevate the second conductive line on the integrated circuit substrate. Depth-of-focus may thereby be improved so that reliability of the conductive lines may also be improved. The second conductive line and the dummy conductive line vertically overlap by an amount that is less than one half the width of the second conductive line. Thus, the capacitance between the second conductive line and the dummy conductive line may be reduced. Undue delay therefore need not be created by introduction of the dummy conductive line.

摘要翻译： 可以通过在第二导线下方形成虚拟导电线来进一步提高集成电路基板上的第二导线，从而减小在集成电路基板上横向隔开的第一和第二升高的导线之间的台阶高度。 因此可以提高聚焦深度，从而也可以提高导电线的可靠性。 第二导线和虚拟导电线垂直重叠的量小于第二导线宽度的一半。 因此，可以减小第二导线与虚拟导电线之间的电容。 因此不需要通过引入虚拟导线来产生不适当的延迟。

公开(公告)号：US06372626B1

公开(公告)日：2002-04-16

申请号：US09361919

申请日：1999-07-27

申请人： Bong-seok Chae ,  Kye-hyun Kyung

发明人： Bong-seok Chae ,  Kye-hyun Kyung

IPC分类号： H01L214763

CPC分类号： H01L23/5222 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： A step height between first and second elevated conductive lines that are laterally spaced apart on an integrated circuit substrate may be reduced by forming a dummy conductive line beneath the second conductive line, to further elevate the second conductive line on the integrated circuit substrate. Depth-of-focus may thereby be improved so that reliability of the conductive lines may also be improved. The second conductive line and the dummy conductive line vertically overlap by an amount that is less than one half the width of the second conductive line. Thus, the capacitance between the second conductive line and the dummy conductive line may be reduced. Undue delay therefore need not be created by introduction of the dummy conductive line.

摘要翻译： 可以通过在第二导线下方形成虚拟导电线来进一步提高集成电路基板上的第二导线，从而减小在集成电路基板上横向隔开的第一和第二升高的导线之间的台阶高度。 因此可以提高聚焦深度，从而也可以提高导电线的可靠性。 第二导线和虚拟导电线垂直重叠的量小于第二导线宽度的一半。 因此，可以减小第二导线与虚拟导电线之间的电容。 因此不需要通过引入虚拟导线来产生不适当的延迟。

公开(公告)号：US07804720B2

公开(公告)日：2010-09-28

申请号：US12614826

申请日：2009-11-09

申请人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

发明人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

IPC分类号： G11C7/10

CPC分类号： G11C5/00 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/222 ,  G11C8/06 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4093

摘要： An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data input/output pins may be further configured to provide data to the memory controller from the memory cell array during a data read operation. A mode register may be configured to store information defining an operational characteristic of the memory device, and the mode register may be configured to be set using the data input/output bus. Related methods, systems, and additional devices are also discussed.

摘要翻译： 集成电路存储器件可以包括存储单元阵列和多个数据输入/输出引脚。 多个数据输入/输出引脚可以被配置为在数据写入操作期间从存储器控制器接收要写入存储单元阵列的数据，并且数据输入/输出引脚还可以被配置为向存储器控制器 在数据读取操作期间从存储单元阵列。 模式寄存器可以被配置为存储定义存储器件的操作特性的信息，并且模式寄存器可以被配置为使用数据输入/输出总线进行设置。 还讨论了相关方法，系统和附加设备。

公开(公告)号：US07636273B2

公开(公告)日：2009-12-22

申请号：US12260373

申请日：2008-10-29

申请人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

发明人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

IPC分类号： G11C8/00

CPC分类号： G11C5/00 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/222 ,  G11C8/06 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4093

摘要： A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation. An enable signal may be provided from the memory controller to a second one of the integrated circuit memory devices over a signal line between the memory controller and the second integrated circuit memory device to thereby enable implementation of the mode register set command for the second integrated circuit memory device during the mode register set operation. Moreover, the disable signal may not be provided to the second integrated circuit memory device during the mode register set operation, and the enable signal may not be provided to the first integrated circuit memory device during the mode register set operation. Related systems, devices and additional methods are also discussed.

摘要翻译： 存储器模块可以包括通过相同的命令/地址总线耦合到存储器控制器的多个存储器件。 控制这种存储器模块的方法可以包括在模式寄存器设置操作期间通过命令/地址总线从存储器控制器向每个集成电路存储器件提供模式寄存器设置命令。 可以通过存储器控制器和第一集成电路存储器件之间的信号线从存储器控制器向集成电路存储器件中的第一个提供禁止信号，从而禁止第一集成电路的模式寄存器设置命令的实现 存储器件在模式寄存器设置操作期间。 可以通过存储器控制器和第二集成电路存储器件之间的信号线从存储器控制器向集成电路存储器件中的第二个提供使能信号，从而能够实现第二集成电路的模式寄存器设置命令 存储器件在模式寄存器设置操作期间。 此外，在模式寄存器设置操作期间，禁止信号可能不被提供给第二集成电路存储器件，并且在模式寄存器设置操作期间可以不向第一集成电路存储器件提供使能信号。 还讨论了相关系统，设备和附加方法。

公开(公告)号：US20080175071A1

公开(公告)日：2008-07-24

申请号：US12058441

申请日：2008-03-28

申请人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

发明人： Kee-hoon Lee ,  Chang-sik Yoo ,  Kye-hyun Kyung

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G06F13/1694 ,  G11C7/10 ,  G11C7/1045 ,  G11C11/4093

摘要： A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.

摘要翻译： 可以提供一种操作包括耦合到命令地址总线的多个存储器件的存储器系统的方法。 特别地，多个存储器件的第一存储器件可以被设置为第一操作模式，并且多个存储器件中的第二存储器件可以被设置为与第一操作模式不同的第二操作模式。 此外，可以响应于通过命令地址总线提供给多个存储器件的读/写命令地址信号执行读/写操作，使得第一存储器件在读/写期间根据第一操作模式进行操作 并且使得第二存储器件在读/写操作期间根据第二操作模式操作。 还讨论了相关系统。

公开(公告)号：US07045892B2

公开(公告)日：2006-05-16

申请号：US10884407

申请日：2004-07-02

申请人： Kye-hyun Kyung

发明人： Kye-hyun Kyung

IPC分类号： H01L29/40

CPC分类号： H01L25/0657 ,  H01L2224/32014 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/4911 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01068 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00014

摘要： Provided is a stack type semiconductor package. The semiconductor package includes a first substrate, a first semiconductor chip, a second substrate, at least one second semiconductor chip and at least one third substrate. The first substrate has external connection terminals mounted on a first surface and a plurality of lands on a second surface that is an opposite side of the first surface. The first semiconductor chip is mounted on the second surface of the first substrate. The second substrate is attached at its first surface to the first semiconductor chip and includes plural outer lands in an outer perimeter of the second surface that is the opposite side of the first surface, a window penetrating between the first and second surface, inner lands around the window of the second surface. The second semiconductor chip is mounted on the second surface of the second substrate. At least one third substrate is attached to the first surface of the second semiconductor chip and includes plural inner lands in the outer perimeter of the second surface that is the opposite side of the first surface, and the window penetrating between the first and second surface, and the inner lands around the window of the second surface. The first and second semiconductor chips have a center pad structure.

摘要翻译： 提供了一种堆叠型半导体封装。 半导体封装包括第一衬底，第一半导体芯片，第二衬底，至少一个第二半导体芯片和至少一个第三衬底。 第一基板具有安装在第一表面上的外部连接端子和与第一表面相对的第二表面上的多个焊盘。 第一半导体芯片安装在第一基板的第二表面上。 第二基板在其第一表面附接到第一半导体芯片，并且包括位于第二表面的与第一表面相反的一侧的外周边中的多个外部凸台，在第一和第二表面之间穿透的窗口， 第二个表面的窗口。 第二半导体芯片安装在第二基板的第二表面上。 至少一个第三衬底附接到第二半导体芯片的第一表面，并且包括位于第二表面的与第一表面相反的一侧的外周中的多个内部平台，并且窗口在第一和第二表面之间穿透， 以及第二表面的窗口周围的内部区域。 第一和第二半导体芯片具有中心焊盘结构。

公开(公告)号：US06940765B2

公开(公告)日：2005-09-06

申请号：US10834490

申请日：2004-04-29

申请人： Kye-hyun Kyung

发明人： Kye-hyun Kyung

IPC分类号： G11C29/04 ,  G11C7/00 ,  G11C29/00

CPC分类号： G11C29/785 ,  G11C29/4401 ,  G11C29/808 ,  G11C2029/1208 ,  G11C2029/4402

摘要： Provided are a repair apparatus and method in a semiconductor memory device, the repair apparatus being selectively programmed suitable for a wafer-level test or a post package test. The repair apparatus includes a repair control circuit, a redundancy memory cell array, and a redundancy decoder. The repair control circuit programs one of an address signal for a first defective cell of the main memory cell array and an address signal for a second defective cell of the main memory cell array and outputs a control signal in response to the address signal undergoing the first decoding operation, the first defective cell being detected during a wafer-level test and the second defective cell being detected during a post package test. The redundancy memory cell array includes a plurality of redundancy memory cells and is activated to repair one of the first and second defective cells. The redundancy decoder is enabled or disabled in response to the control signal and is enabled to activate parts of the redundancy memory cells. The normal decoder is disabled in response to the control signal when the redundancy decoder is enabled.

公开(公告)号：US06834014B2

公开(公告)日：2004-12-21

申请号：US10199857

申请日：2002-07-19

申请人： Chang-sik Yoo ,  Kye-hyun Kyung

发明人： Chang-sik Yoo ,  Kye-hyun Kyung

IPC分类号： G11C1604

CPC分类号： G11C7/1066 ,  G11C7/10 ,  G11C7/1045 ,  G11C11/4093

摘要： An integrated circuit memory device for use in a memory system receives predetermined command/address signals from a memory controller and reads and writes data in response to the command/address signals. The memory device includes at least one input/output terminal that inputs/outputs data from/to the memory controller via a data input/output bus, at least one termination resistor, and an active termination control signal generator that generates a control signal to control active termination of the at least one data input/output terminal in response to a chip selection signal from the memory controller. The memory device also includes at least one switch coupled in series with the at least one termination resistor between the at least one input/output terminal and a predetermined voltage wherein the at least one switch is switched on/off in response to the control signal such that the at least one input/output terminal is connected/disconnected to/from the predetermined voltage responsive to the control signal and such that the at least one termination resistor is coupled in series between the predetermined voltage and the at least one input/output terminal when the at least one switch is switched on and such that the at least one input/output terminal is decoupled from the predetermined voltage when the at least one switch is switched off. Related memory systems and methods are also discussed.

摘要翻译： 用于存储器系统的集成电路存储器装置从存储器控制器接收预定的命令/地址信号，并响应于命令/地址信号读取和写入数据。 存储器件包括至少一个输入/输出端子，其通过数据输入/输出总线，至少一个终端电阻器和产生控制信号的有源终端控制信号发生器来输入/输出数据到存储器控制器 响应于来自存储器控制器的芯片选择信号，主动终止至少一个数据输入/输出终端。 存储器件还包括至少一个开关，其与至少一个输入/输出端子与预定电压之间的至少一个终端电阻器串联耦合，其中至少一个开关响应于控制信号而被接通/断开 所述至少一个输入/输出端子响应于所述控制信号而与所述预定电压连接/断开，并且使得所述至少一个终端电阻串联在所述预定电压和所述至少一个输入/输出端子之间 当所述至少一个开关被接通时，并且当所述至少一个开关被切断时，所述至少一个输入/输出端与所述预定电压分离。 还讨论了相关的内存系统和方法。

公开(公告)号：US6078536A

公开(公告)日：2000-06-20

申请号：US207534

申请日：1998-12-08

申请人： Byung-sick Moon ,  Kye-hyun Kyung ,  Sung-joo Lee

发明人： Byung-sick Moon ,  Kye-hyun Kyung ,  Sung-joo Lee

IPC分类号： G11C11/34 ,  G11C5/06 ,  G11C11/401 ,  G11C29/12 ,  G11C29/48 ,  G11C7/00

CPC分类号： G11C29/48 ,  G11C5/066

摘要： An integrated circuit memory device and method including a direct mode assigns internal data and address signals to separate pins. In particular, a plurality of first pins is assigned to the plurality of internal data signals that provide the data to the memory array in direct test mode. A plurality of second pins is assigned to the plurality of internal address signals that provide the address to the memory array in direct test mode, wherein none of the pins included in first plurality of pins are included in the second plurality of pins.

摘要翻译： 包括直接模式的集成电路存储器件和方法将内部数据和地址信号分配给单独的引脚。 特别地，将多个第一引脚分配给在直接测试模式下将数据提供给存储器阵列的多个内部数据信号。 多个第二引脚被分配给在直接测试模式下向存储器阵列提供地址的多个内部地址信号，其中包括在第一多个引脚中的引脚都不包括在第二多个引脚中。

公开(公告)号：US08477546B2

公开(公告)日：2013-07-02

申请号：US12656430

申请日：2010-01-29

申请人： Kye-hyun Kyung

发明人： Kye-hyun Kyung

IPC分类号： G11C7/00

CPC分类号： G11C29/808

摘要： A semiconductor memory device includes a plurality of memory areas. Each of the memory areas includes a normal cell array and a redundancy cell array for repairing defective cells generated in the normal cell array such that the semiconductor memory device is usable even when memory arrays include defective cells. A size of a redundancy cell array of a first memory area is greater than a size of the redundancy cell arrays of the other memory areas.

摘要翻译： 半导体存储器件包括多个存储区域。 每个存储区域包括正常单元阵列和用于修复在正常单元阵列中产生的有缺陷单元的冗余单元阵列，使得半导体存储器件即使当存储器阵列包括有缺陷单元时也是可用的。 第一存储区域的冗余单元阵列的大小大于其他存储区域的冗余单元阵列的大小。