公开(公告)号：US20050255699A1

公开(公告)日：2005-11-17

申请号：US10709534

申请日：2004-05-12

申请人： Bradley Jones ,  Christian Lavoie ,  Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

发明人： Bradley Jones ,  Christian Lavoie ,  Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

IPC分类号： H01L21/20 ,  H01L21/285 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L29/78

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/7833

摘要： A method for forming a metal suicide contact for a semiconductor device includes forming a refractory metal layer over a substrate, including active and non-active area of said substrate, and forming a cap layer over the refractory metal layer. A counter tensile layer is formed over the cap layer, wherein the counter tensile layer is selected from a material such that an opposing directional stress is created between the counter tensile layer and the cap layer, with respect to a directional stress created between the refractory metal layer and the cap layer.

摘要翻译： 用于形成用于半导体器件的金属硅化物接触的方法包括在包括所述衬底的有源和非有源区域的衬底上形成难熔金属层，并在难熔金属层上形成覆盖层。 反面拉伸层形成在覆盖层上方，其中相对抗拉层选自材料，使得在相对拉伸层和盖层之间产生相对的方向应力，相对于难熔金属之间产生的方向应力 层和盖层。

公开(公告)号：US06436823B1

公开(公告)日：2002-08-20

申请号：US09679738

申请日：2000-10-05

申请人： Cyril Cabral, Jr. ,  Chung-Ping Eng ,  Lynne Marie Gignac ,  Christian Lavoie ,  Patricia O'Neil ,  Kirk David Peterson ,  Tina Wagner ,  Yun-Yu Wang ,  Keith Wong

发明人： Cyril Cabral, Jr. ,  Chung-Ping Eng ,  Lynne Marie Gignac ,  Christian Lavoie ,  Patricia O'Neil ,  Kirk David Peterson ,  Tina Wagner ,  Yun-Yu Wang ,  Keith Wong

IPC分类号： H01L2144

CPC分类号： H01L21/76856 ,  H01L21/28518 ,  H01L2221/1078

摘要： A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti—Si—Co which produces weakly bonded Ti which reacts with fluorine atoms from WF6 during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material. The maximum thickness of the amorphous material layer formed by the present invention method is less than 5 nm which minimizes the line failure problem.

摘要翻译： 提供了一种在半导体结构中的金属硅化物层的顶部上形成TiN层的方法，而不形成含有Ti，Co和Si的厚非晶层以及形成的结构。 在该方法中，在金属硅化物层的顶部沉积Ti层之后，进行双相退火工艺，其中在不高于500℃的温度下在成形气体（或氨）中进行低温退火。 首先进行少于2小时，然后在不低于500℃的第二温度下在含氮气体（或氨）中进行低温退火2小时以形成TiN层。 本发明的方法防止了在随后的CVD W沉积过程中由Ti-Si-Co的厚的无定形材料层产生的弱结合的Ti与来自WF6的氟原子反应而产生的弱结合的问题，并导致由于体积膨胀引起的衬管故障 无定形材料。 通过本发明方法形成的非晶材料层的最大厚度小于5nm，这使线路故障问题最小化。

公开(公告)号：US20080020535A1

公开(公告)日：2008-01-24

申请号：US11866751

申请日：2007-10-03

申请人： Levent Gulari ,  Kevin Mello ,  Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

发明人： Levent Gulari ,  Kevin Mello ,  Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L29/665

摘要： A silicide cap structure and method of fabricating a silicide cap having a low sheet resistance. The method provides a semiconductor substrate and a MOSFET structure comprising a gate insulator on the substrate, an Si-containing gate electrode on the gate insulator layer, and source/drain diffusions. Atop the gate electrode and source/drain diffusions is formed a layer of metal used in forming a silicide region atop the transistor gate electrode and diffusions; an intermediate metal barrier layer formed atop the silicide forming metal layer; and, an oxygen barrier layer formed atop the intermediate metal barrier layer. As a result of annealing the MOSFET structure, resulting formed silicide regions exhibit a lower sheet resistance. As the intermediate metal barrier layer comprises a material exhibiting tensile stress, the oxygen barrier layer may comprise a compressive material for minimizing a total mechanical stress of the cap structure and underlying layers during the applied anneal.

摘要翻译： 一种硅化物盖结构和制造具有低薄层电阻的硅化物盖的方法。 该方法提供半导体衬底和MOSFET结构，其包括在衬底上的栅极绝缘体，栅极绝缘体层上的含Si栅极电极和源极/漏极扩散。 在栅电极和源极/漏极扩散之上形成用于在晶体管栅极顶部形成硅化物区域和扩散的金属层; 形成在所述硅化物形成金属层顶上的中间金属阻挡层; 以及形成在中间金属阻挡层顶上的氧阻隔层。 作为对MOSFET结构进行退火的结果，所形成的形成的硅化物区域具有较低的薄层电阻。 当中间金属阻挡层包括显示拉伸应力的材料时，氧阻挡层可以包括用于在施加的退火期间最小化盖结构和下层的总机械应力的压缩材料。

公开(公告)号：US20070020929A1

公开(公告)日：2007-01-25

申请号：US11460671

申请日：2006-07-28

申请人： Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

发明人： Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of metal rich portions of the metal layer is reduced through the introduction of silicon thereto, and the semiconductor device is annealed.

摘要翻译： 用于减少半导体器件的自对准硅化物工艺中的枝晶形成的方法包括在半导体衬底上形成硅化物金属层，所述半导体器件具有一个或多个扩散区域，一个或多个隔离区域和一个或多个栅极结构 形成在其上。 金属层的富金属部分的浓度通过向其中引入硅而降低，半导体器件退火。

公开(公告)号：US20060163671A1

公开(公告)日：2006-07-27

申请号：US10905949

申请日：2005-01-27

申请人： Levent Gulari ,  Kevin Mello ,  Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

发明人： Levent Gulari ,  Kevin Mello ,  Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L29/665

摘要： A suicide cap structure and method of fabricating a suicide cap having a low sheet resistance. The method provides a semiconductor substrate and a MOSFET structure comprising a gate insulator on the substrate, an Si-containing gate electrode on the gate insulator layer, and source/drain diffusions. Atop the gate electrode and source/drain diffusions is formed a layer of metal used in forming a silicide region atop the transistor gate electrode and diffusions; an intermediate metal barrier layer formed atop the silicide forming metal layer; and, an oxygen barrier layer formed atop the intermediate metal barrier layer. As a result of annealing the MOSFET structure, resulting formed silicide regions exhibit a lower sheet resistance. As the intermediate metal barrier layer comprises a material exhibiting tensile stress, the oxygen barrier layer may comprise a compressive material for minimizing a total mechanical stress of the cap structure and underlying layers during the applied anneal.

摘要翻译： 一种自杀帽结构和制造具有低薄层阻力的自杀帽的方法。 该方法提供半导体衬底和MOSFET结构，其包括在衬底上的栅极绝缘体，栅极绝缘体层上的含Si栅极电极和源极/漏极扩散。 在栅电极和源极/漏极扩散之上形成用于在晶体管栅极顶部形成硅化物区域和扩散的金属层; 形成在所述硅化物形成金属层顶上的中间金属阻挡层; 以及形成在中间金属阻挡层顶上的氧阻隔层。 作为对MOSFET结构进行退火的结果，所形成的形成的硅化物区域具有较低的薄层电阻。 当中间金属阻挡层包括显示拉伸应力的材料时，氧阻挡层可以包括用于在施加的退火期间最小化盖结构和下层的总机械应力的压缩材料。

公开(公告)号：US20070210448A1

公开(公告)日：2007-09-13

申请号：US11308186

申请日：2006-03-10

申请人： Keith Wong ,  Yun-Yu Wang ,  Horatio Wildman ,  Christopher Parks ,  Chih-Chao Yang

发明人： Keith Wong ,  Yun-Yu Wang ,  Horatio Wildman ,  Christopher Parks ,  Chih-Chao Yang

IPC分类号： H01L23/48

CPC分类号： H01L23/485 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure that includes a Co-containing liner disposed between an oxygen-getter layer and a metal-containing conductive material is provided. The Co-containing liner, the oxygen-getter layer and the metal-containing conductive material form MOL metallurgy where the Co-containing liner replaces a traditional TiN liner. By “Co-containing” is meant that the liner includes elemental Co alone or elemental Co and at least one of P or B. In order to provide better step coverage of the inventive Co-containing liner within a high aspect ratio contact opening, the Co-containing liner is formed via an electroless deposition process.

摘要翻译： 提供了包括设置在吸氧剂层和含金属的导电材料之间的含Co衬里的半导体结构。 含Co的内衬，吸氧剂层和含金属的导电材料形成MOL冶金，其中含Co衬垫代替了传统的TiN衬里。 “含Co”是指衬垫包括元素Co单体或元素Co以及P或B中的至少一种。为了在高纵横比接触开口内提供本发明的含Co衬垫的更好的台阶覆盖， 通过无电镀沉积工艺形成含钴内衬。

公开(公告)号：US20060270245A1

公开(公告)日：2006-11-30

申请号：US10908833

申请日：2005-05-27

申请人： Richard Conti ,  Thomas Houghton ,  Michael Lofaro ,  Jeffery Maxson ,  Ann McDonald ,  Yun-Yu Wang ,  Keith Wong ,  Daewon Yang

发明人： Richard Conti ,  Thomas Houghton ,  Michael Lofaro ,  Jeffery Maxson ,  Ann McDonald ,  Yun-Yu Wang ,  Keith Wong ,  Daewon Yang

IPC分类号： H01L21/31

CPC分类号： H01L23/53238 ,  H01L21/28556 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.

摘要翻译： 本发明涉及一种用于互连结构的双层盖结构，其包括铜金属化或其它导电金属化。 这种双层盖结构包括通过无偏高密度等离子体（HDP）化学气相沉积工艺形成的第一盖层和在第一盖层上的第二盖层，其中第二盖层由偏置的高密度等离子体（bHDP ）化学气相沉积工艺。 在bHDP化学气相沉积工艺期间，将低AC偏置功率施加到衬底上以增加衬底表面上的离子轰击并引起封盖材料的再溅射，从而形成具有优异的反应离子蚀刻（RIE）的无缝第二帽层 ）选择性。

公开(公告)号：US20060001162A1

公开(公告)日：2006-01-05

申请号：US11084724

申请日：2005-03-18

申请人： Ronald Schutz ,  Werner Robl ,  Rajeev Malik ,  Lawrence Clevenger ,  Oleg Gluschenkov ,  Cyril Cabral ,  Roy Iggulden ,  Yun-Yu Wang ,  Keith Wong ,  Irene McStay

发明人： Ronald Schutz ,  Werner Robl ,  Rajeev Malik ,  Lawrence Clevenger ,  Oleg Gluschenkov ,  Cyril Cabral ,  Roy Iggulden ,  Yun-Yu Wang ,  Keith Wong ,  Irene McStay

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/7685 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/76838 ,  H01L21/76855 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4941 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L2221/1078

摘要： A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.

摘要翻译： 提供集成电路（12）中的导电结构和形成该结构的方法，其包括多晶硅层（30），在多晶硅上含有钛的薄层，在钛 - 钛层上的氮化钨层（34） 并且在氮化钨层上形成钨层。 该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。 该结构经受高温处理，而在多晶硅层（30）和钨层（32）中基本不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

公开(公告)号：US20070077760A1

公开(公告)日：2007-04-05

申请号：US11163038

申请日：2005-10-03

申请人： Keith Wong ,  Robert Purtell

发明人： Keith Wong ,  Robert Purtell

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  C23C14/16 ,  C23C14/32 ,  C23C14/345 ,  H01L21/28052 ,  H01L21/2855 ,  H01L29/66507 ,  H01L29/78

摘要： A method and apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of an annular electrode (e.g. a Ni ring) connected to an RF generator. Material is deposited non-directionally on the substrate in the absence of the secondary plasma and electrical biasing of the substrate, and deposited directionally when the secondary plasma is present and the substrate is electrically biased. Nickel silicide formed from the deposited metal has a lower gate polysilicon sheet resistance and may have a lower density of pipe defects than NiSi formed from metal deposited in a solely directional process, and has a lower source/drain contact resistance than NiSi formed from metal deposited in a solely non-directional process.

摘要翻译： 提供了一种方法和装置，其中在相同的处理室中执行非定向和定向金属（例如Ni）沉积步骤。 形成第一等离子体以从靶中去除材料; 在连接到RF发生器的环形电极（例如Ni环）的内部形成用于增加材料中的离子密度的二次等离子体。 在不存在基板的二次等离子体和电偏置的情况下，材料被非定向地沉积在基板上，并且当存在二次等离子体并且基板被电偏置时定向沉积材料。 由沉积金属形成的硅化镍具有较低的栅极多晶硅薄层电阻，并且可能具有比仅在单向定向工艺中沉积的金属形成的NiSi更低的管缺陷密度，并且具有比由金属沉积形成的NiSi更低的源/漏接触电阻 在一个单一的无方向的过程。

公开(公告)号：US20070161240A1

公开(公告)日：2007-07-12

申请号：US11306719

申请日：2006-01-09

申请人： Robert Purtell ,  Keith Wong

发明人： Robert Purtell ,  Keith Wong

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/7833

摘要： Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance. Additionally, the method allows such a tensile silicide region to be formed using a relatively thin first metal layer-protective cap layer-second metal layer stack, and particularly, a relatively thin second metal layer, to minimize mechanical energy build up at the junctions between the gate conductor and the sidewall spacers to avoid silicon bridging.

摘要翻译： 公开了一种用于调整硅化物应力的结构和方法，特别是用于在n-FET的栅极导体上形成拉伸硅化物区域，以优化n-FET性能。 更具体地，在n-FET结构上形成第一金属层保护盖层 - 第二金属层堆叠。 然而，在沉积第二金属层之前，保护层暴露于空气中。 这种空气破碎步骤改变了保护盖层和第二金属层之间的粘附，从而在硅化物形成期间实现施加在第一金属层上的应力。 结果是对于n-FET性能最佳的更强的硅化物。 此外，该方法允许使用相对较薄的第一金属层 - 保护层 - 第二金属层堆叠形成这种拉伸硅化物区域，特别是相对较薄的第二金属层，以最小化在 栅极导体和侧壁间隔件，以避免硅桥接。