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    Low cost solar cell manufacture method employing a reusable substrate
    3.
    发明授权
    Low cost solar cell manufacture method employing a reusable substrate 失效
    低成本太阳能电池制造方法采用可重复使用的基板

    公开(公告)号：US08609453B2

    公开(公告)日：2013-12-17

    申请号：US12951601

    申请日：2010-11-22

    申请人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

    发明人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

    IPC分类号： H01L21/00

    CPC分类号： H01L31/186 ,  H01L31/0248 ,  H01L31/068 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

    摘要： A reusable substrate and method for forming single crystal silicon solar cells are described. A method of forming a photovoltaic cell includes forming an intermediate layer on a monocrystalline silicon substrate, forming a monocrystalline silicon layer on the intermediate layer, and forming electrical features in the monocrystalline silicon layer. The method further includes forming openings in the monocrystalline silicon layer, and detaching the monocrystalline silicon layer from the substrate by selectively etching the intermediate layer through the openings.

    摘要翻译： 描述了可重复使用的基板和用于形成单晶硅太阳能电池的方法。 形成光伏电池的方法包括在单晶硅衬底上形成中间层，在中间层上形成单晶硅层，并在单晶硅层中形成电特征。 该方法还包括在单晶硅层中形成开口，并且通过选择性地通过开口蚀刻中间层，从而将单晶硅层从衬底上分离出来。

    CONTACT BARS FOR MODIFYING STRESS IN SEMICONDUCTOR DEVICE AND RELATED METHOD
    4.
    发明申请
    CONTACT BARS FOR MODIFYING STRESS IN SEMICONDUCTOR DEVICE AND RELATED METHOD 审中-公开
    用于修改半导体器件中的应力的接触棒及相关方法

    公开(公告)号：US20130240997A1

    公开(公告)日：2013-09-19

    申请号：US13424319

    申请日：2012-03-19

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  Edward J. Nowak

    IPC分类号： H01L27/11 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L27/1104 ,  H01L29/7843

    摘要： Solutions for forming stress optimizing contact bars and contacts are disclosed. In one aspect, a semiconductor device is disclosed including an n-type field effect transistor (NFET) having source/drain regions; a p-type field effect transistor (PFET) having source/drain regions; a stress inducing layer over both the NFET and the PFET, the stress inducing layer inducing only one of a compressive stress and a tensile stress; a contact bar extending through the stress inducing layer and coupled to at least one of the source/drain regions of a selected device of the PFET and the NFET to modify a stress induced in the selected device compared to a stress induced in the other device; and a round contact extending through the stress inducing layer and coupled to at least one of the source/drain regions of the other device of the PFET and the NFET.

    摘要翻译： 公开了用于形成应力优化接触棒和触点的解决方案。 一方面，公开了一种具有源极/漏极区域的n型场效应晶体管（NFET）的半导体器件; 具有源极/漏极区域的p型场效应晶体管（PFET） 在NFET和PFET两者上的应力诱导层，应力诱导层仅引起压缩应力和拉伸应力之一; 接触棒延伸穿过应力感应层并且耦合到PFET和NFET的所选器件的源/漏区中的至少一个，以修改与在另一器件中感应的应力相比在所选器件中感应的应力; 以及延伸穿过应力感应层并且耦合到PFET和NFET的另一个器件的源极/漏极区域中的至少一个的圆形接触。

    Strained semiconductor devices and methods of fabricating strained semiconductor devices
    6.
    发明授权
    Strained semiconductor devices and methods of fabricating strained semiconductor devices 有权
    应变半导体器件和制造应变半导体器件的方法

    公开(公告)号：US08445965B2

    公开(公告)日：2013-05-21

    申请号：US12940115

    申请日：2010-11-05

    申请人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

    发明人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

    IPC分类号： H01L27/12

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203

    摘要： A structure and method of fabricating the structure. The structure includes a first region of a semiconductor substrate separated from a second region of the semiconductor substrate by trench isolation formed in the substrate; a first stressed layer over the first region; a second stressed layer over second region; the first stressed layer and second stressed layer separated by a gap; and a passivation layer on the first and second stressed layers, the passivation layer extending over and sealing the gap.

    摘要翻译： 一种制造结构的结构和方法。 该结构包括半导体衬底的第一区域，其通过在衬底中形成的沟槽隔离与半导体衬底的第二区域分离; 第一个区域的第一个应力层; 在第二区域的第二个应力层; 第一应力层和第二应力层由间隙分开; 以及在第一和第二应力层上的钝化层，钝化层延伸并密封间隙。

    Dense pitch bulk FinFET process by selective EPI and etch
    7.
    发明授权
    Dense pitch bulk FinFET process by selective EPI and etch 有权
    通过选择性EPI和蚀刻的密集体积FinFET工艺

    公开(公告)号：US08420471B2

    公开(公告)日：2013-04-16

    申请号：US13103569

    申请日：2011-05-09

    申请人： Brent A. Anderson ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Edward J. Nowak

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/84 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78609 ,  Y10S257/903

    摘要： Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate may be formed. In another embodiment a gate conductor between the fins contacts a conductor layer on the bulk wafer so a back gate may be formed. In yet another embodiment both of the previous structures are simultaneously formed on the same bulk wafer. The method allow the pairs of transistors to be formed with a variety of features.

    摘要翻译： 公开了通过在体晶片上的硅锗翅片上外延生长一对硅散热片来形成一对晶体管的方法。 在一个实施例中，翅片之间的栅极导体与体晶片上的导体层隔离，因此可以形成前栅极。 在另一个实施例中，翅片之间的栅极导体接触体晶片上的导体层，因此可形成背栅。 在另一个实施例中，两个先前的结构同时形成在相同的体晶片上。 该方法允许成对的晶体管具有各种特征。

    Method for Fabricating Field Effect Transistor Devices with High-Aspect Ratio Mask
    8.
    发明申请
    Method for Fabricating Field Effect Transistor Devices with High-Aspect Ratio Mask 失效
    制造具有高比例掩模的场效应晶体管器件的方法

    公开(公告)号：US20130065370A1

    公开(公告)日：2013-03-14

    申请号：US13229154

    申请日：2011-09-09

    申请人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

    发明人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6653 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/785

    摘要： A method for forming feature on a substrate includes forming at least one layer of a feature material on a substrate, patterning a photolithographic resist material on the at least one layer of the feature material, removing portions of the feature material to define a feature, depositing a masking material layer over the resist material and exposed regions of the substrate, modifying a portion of the substrate, and removing the masking material layer and the resist material.

    摘要翻译： 在衬底上形成特征的方法包括在衬底上形成至少一层特征材料，在特征材料的至少一层上图案化光刻抗蚀剂材料，去除特征材料的部分以限定特征，沉积 在抗蚀剂材料上的掩模材料层和衬底的暴露区域，修改衬底的一部分，以及去除掩模材料层和抗蚀剂材料。

    ISOLATION REGION FABRICATION FOR REPLACEMENT GATE PROCESSING
    9.
    发明申请
    ISOLATION REGION FABRICATION FOR REPLACEMENT GATE PROCESSING 有权
    用于替代浇口加工的隔离区制造

    公开(公告)号：US20130043535A1

    公开(公告)日：2013-02-21

    申请号：US13213713

    申请日：2011-08-19

    申请人： Brent A. Anderson ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Edward J. Nowak

    IPC分类号： H01L21/762 ,  H01L27/12

    CPC分类号： H01L29/66545 ,  H01L21/28123 ,  H01L21/76283 ,  H01L21/84

    摘要： A method for isolation region fabrication for replacement gate integrated circuit (IC) processing includes forming a plurality of dummy gates on a substrate; forming a block mask over the plurality of dummy gates, such that the block mask selectively exposes a dummy gate of the plurality of dummy gates; removing the exposed dummy gate to form an isolation region recess corresponding to the removed dummy gate; filling the isolation region recess with an insulating material to form an isolation region; removing the block mask to expose a remaining plurality of dummy gates; and performing replacement gate processing on the remaining plurality of dummy gates to form a plurality of active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region.

    摘要翻译： 用于替换栅极集成电路（IC）处理的隔离区域制造的方法包括在衬底上形成多个虚拟栅极; 在所述多个虚拟栅极上形成块掩模，使得所述块掩模选择性地暴露所述多个伪栅极的伪栅极; 去除所暴露的虚拟栅极以形成对应于去除的虚拟栅极的隔离区域凹部; 用绝缘材料填充隔离区域凹部以形成隔离区域; 去除所述块掩模以暴露剩余的多个伪栅极; 以及对剩余的多个伪栅极执行替换栅极处理以形成多个有源器件，其中所述多个有源器件中的至少两个通过所述隔离区域彼此电隔离。

    Field effect transistor with channel region edge and center portions having different band structures for suppressed corner leakage
    10.
    发明授权
    Field effect transistor with channel region edge and center portions having different band structures for suppressed corner leakage 有权
    场效应晶体管，沟道区域边缘和中心部分具有不同的带结构，用于抑制拐角泄漏

    公开(公告)号：US08350343B2

    公开(公告)日：2013-01-08

    申请号：US13362019

    申请日：2012-01-31

    申请人： Brent A. Anderson ,  Edward J. Nowak

    发明人： Brent A. Anderson ,  Edward J. Nowak

    IPC分类号： H01L29/76

    CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/0661 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/785

    摘要： Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.

    摘要翻译： 作为通道材料带边调制的函数，公开了具有抑制的副阈值拐角泄漏的场效应晶体管（FET）的实施例。 具体地说，与中心相比，FET沟道区在边缘形成不同的材料。 选择具有不同带结构和这些材料的特定位置的不同材料，以便有效地提高沟道区域相对于沟道区域中心处的Vt的边缘处的阈值电压（Vt），从而抑制子 阈值角泄漏。 还公开了用于这种FET的设计结构和用于形成这种FET的方法实施例。