公开(公告)号：US08492214B2

公开(公告)日：2013-07-23

申请号：US13051510

申请日：2011-03-18

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L21/338

CPC分类号： H01L31/0232 ,  G06F17/5045 ,  G06F17/5054 ,  H01L27/14632 ,  H01L27/14683 ,  H01L29/66545

摘要： Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses.

摘要翻译： 提供了具有镶嵌金属栅极和像素传感器单元屏蔽的半导体结构，制造方法和设计结构。 该方法包括在虚拟栅极结构上形成介电层。 该方法还包括在电介质层中形成一个或多个凹槽。 该方法还包括去除电介质层中的虚拟栅极结构以形成沟槽。 该方法还包括在沟槽中形成金属和在电介质层中形成多个凹槽以在沟槽中形成镶嵌金属栅极结构以及在一个或多个凹槽中形成一个或多个金属部件。

公开(公告)号：US20120181588A1

公开(公告)日：2012-07-19

申请号：US13005650

申请日：2011-01-13

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L31/113 ,  G06F17/50 ,  H01L31/18

CPC分类号： H01L27/14614 ,  H01L27/14689

摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. A transistor in the pixel sensor cell has a gate structure that includes a gate dielectric with a thick region and a thin region. A gate electrode of the gate structure is formed on the thick region of the gate dielectric and the thin region of the gate dielectric. The thick region of the gate dielectric and the thin region of the gate dielectric provide the transistor with an asymmetric threshold voltage.

摘要翻译： 像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。 像素传感器单元中的晶体管具有包括具有厚区域和薄区域的栅极电介质的栅极结构。 栅极结构的栅电极形成在栅极电介质的厚区域和栅极电介质的薄区域上。 栅极电介质的厚区域和栅极电介质的薄区为晶体管提供非对称阈值电压。

公开(公告)号：US07790611B2

公开(公告)日：2010-09-07

申请号：US11749898

申请日：2007-05-17

申请人： Brent A. Anderson ,  John J. Ellis-Monaghan ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Brent A. Anderson ,  John J. Ellis-Monaghan ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21/44

CPC分类号： H01L21/76885 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76867 ,  H01L21/76895 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension).

摘要翻译： 一种用于形成适用于FEOL和BEOL半导体制造应用的亚光刻尺寸的导电结构的方法。 该方法包括在衬底上形成含硅材料的形貌特征; 在地形特征上形成介电帽; 施加掩模结构以暴露所述地形特征的侧壁上的图案，所述暴露图案对应于要形成的导电结构; 在所述侧壁的暴露部分处沉积金属并在所述暴露的侧壁部分处形成一个或多个金属硅化物导电结构; 去除所述电介质盖层; 并去除含硅的地形特征。 结果是形成一个或多个金属硅化物导体结构，其形成用于单个光刻定义的特征。 在示例性实施例中，形成的金属硅化物导电结构具有高纵横比，例如从1：1至20：1（高度与宽度尺寸）。

公开(公告)号：US20090101978A1

公开(公告)日：2009-04-23

申请号：US11873521

申请日：2007-10-17

申请人： Brent A. Anderson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.

摘要翻译： 这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的设计结构的实施例，其中多个散热片部分或完全由高导电材料 （例如，金属硅化物）。 以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。 以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。

公开(公告)号：US20090065834A1

公开(公告)日：2009-03-12

申请号：US11850798

申请日：2007-09-06

申请人： Brent A. Anderson ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L27/146

CPC分类号： H01L27/14636 ,  H01L27/14625

摘要： A CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical functions. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect.

摘要翻译： 一种包括有源像素单元阵列的CMOS图像传感器。 每个有源像素单元包括衬底; 形成在基板表面处或下方的光敏装置，用于响应于入射光收集电荷载体; 以及形成在光敏器件上方的一个或多个透光导线结构，所述一个或多个导电线结构位于光敏器件上方的光路中。 形成的透光导线结构提供电和光学功能。 通过根据像素配色方案调整导线层的厚度以过滤光，提供光学功能。 或者，透光导线结构可以形成为提供光聚焦功能的微透镜结构。 用于导线层的电气功能包括用作电容器板，电阻器或互连件。

公开(公告)号：US20080284021A1

公开(公告)日：2008-11-20

申请号：US11749898

申请日：2007-05-17

申请人： Brent A. Anderson ,  John J. Ellis-Monaghan ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Brent A. Anderson ,  John J. Ellis-Monaghan ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76885 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76867 ,  H01L21/76895 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension).

摘要翻译： 一种用于形成适用于FEOL和BEOL半导体制造应用的亚光刻尺寸的导电结构的方法。 该方法包括在衬底上形成含硅材料的形貌特征; 在地形特征上形成介电帽; 施加掩模结构以暴露所述地形特征的侧壁上的图案，所述暴露图案对应于要形成的导电结构; 在所述侧壁的暴露部分处沉积金属并在所述暴露的侧壁部分处形成一个或多个金属硅化物导电结构; 去除所述电介质盖层; 并去除含硅的地形特征。 结果是形成一个或多个金属硅化物导体结构，其形成用于单个光刻定义的特征。 在示例性实施例中，形成的金属硅化物导电结构具有高纵横比，例如从1：1至20：1（高度与宽度尺寸）。

公开(公告)号：US07661077B2

公开(公告)日：2010-02-09

申请号：US11850807

申请日：2007-09-06

申请人： Brent A. Anderson ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： G06F17/50 ,  H01L27/146

CPC分类号： H01L27/14627 ,  H01L27/14621 ,  H01L27/14636

摘要： A design structure embodied in a machine readable medium for use in a design process, the design structure representing a CMOS image sensor device comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical functions. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect.

摘要翻译： 体现在用于设计过程的机器可读介质中的设计结构，该设计结构表示包括有源像素单元阵列的CMOS图像传感器设备。 每个有源像素单元包括衬底; 形成在基板表面处或下方的光敏装置，用于响应于入射光收集电荷载体; 以及形成在光敏器件上方的一个或多个透光导线结构，所述一个或多个导电线结构位于光敏器件上方的光路中。 形成的透光导线结构提供电和光学功能。 通过根据像素配色方案调整导线层的厚度以过滤光，提供光学功能。 或者，透光导线结构可以形成为提供光聚焦功能的微透镜结构。 用于导线层的电气功能包括用作电容器板，电阻器或互连件。

公开(公告)号：US20090298220A1

公开(公告)日：2009-12-03

申请号：US11850801

申请日：2007-09-06

申请人： Brent A. Anderson ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L31/18 ,  H04N5/335

CPC分类号： H01L27/14636 ,  H04N5/374

摘要： A method of fabricating a CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical function. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect.

摘要翻译： 一种制造包括有源像素单元阵列的CMOS图像传感器的方法。 每个有源像素单元包括衬底; 形成在基板表面处或下方的光敏装置，用于响应于入射光收集电荷载体; 以及形成在光敏器件上方的一个或多个透光导线结构，所述一个或多个导电线结构位于光敏器件上方的光路中。 形成的透光导线结构提供电和光学功能。 通过根据像素配色方案调整导线层的厚度以过滤光，提供光学功能。 或者，透光导线结构可以形成为提供光聚焦功能的微透镜结构。 用于导线层的电气功能包括用作电容器板，电阻器或互连件。

公开(公告)号：US20090020819A1

公开(公告)日：2009-01-22

申请号：US11778217

申请日：2007-07-16

申请人： Brent A. Anderson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.

摘要翻译： 这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的实施例，其中多个散热片部分或完全由高导电材料（例如， 金属硅化物）。 以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。 以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。

公开(公告)号：US20120211854A1

公开(公告)日：2012-08-23

申请号：US13029670

申请日：2011-02-17

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L31/0352 ,  G06F17/50 ,  H01L31/18

CPC分类号： H01L27/14614

摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.

摘要翻译： 像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。 像素传感器单元具有在栅极电介质上包括栅极电介质和栅电极的栅极结构。 栅极电极包括具有在栅极电介质上具有并置关系的第一和第二部分的层。 栅电极的第二部分由诸如掺杂多晶硅或金属的导体组成。 栅电极的第一部分由具有比包括第二部分的导体更高的功函的金属组成，使得栅极结构具有非对称阈值电压。