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    Device initiated partial system quiescing
    1.
    发明授权
    Device initiated partial system quiescing 失效
    设备启动部分系统停顿

    公开(公告)号：US4970640A

    公开(公告)日：1990-11-13

    申请号：US251969

    申请日：1988-09-26

    申请人： Brent C. Beardsley ,  Eugene P. Hefferon ,  Kenneth R. Lynch ,  Stephen W. Schimke ,  Lloyd R. Shipman, Jr. ,  Susan M. Wethington

    发明人： Brent C. Beardsley ,  Eugene P. Hefferon ,  Kenneth R. Lynch ,  Stephen W. Schimke ,  Lloyd R. Shipman, Jr. ,  Susan M. Wethington

    IPC分类号： G06F11/14 ,  G06F11/20

    CPC分类号： G06F11/2005 ,  G06F11/142 ,  G06F11/20

    摘要： A data processing system includes a plurality of host systems and peripheral subsystems, particularly data storage subsystems. Each of the data storage subsystems includes a plurality of control units attaching a plurality of data storage devices such as direct access storage devices (DASD) for storing data on behalf of the various host systems. Each of the control units have a separate storage path for accessing the peripheral data storage devices using dynamic pathing. The storage paths can be clustered into power clusters. Maintenance personnel acting through maintenance panels on either the control units or the peripheral data storage devices activate the subsystem to request reconfiguration of the subsystem from all of the host systems connected top the subsystem. The host systems can honor the request or reject it based upon diverse criteria. Upon each of the host systems approving the reconfiguration, the subsystem 13 is reconfigured for maintenance purposes. Upon completion of the maintenance procedures, a second reconfiguration request is sent to the host systems for causing quiesce devices to resume normal operations.

    摘要翻译： 数据处理系统包括多个主机系统和外围子系统，特别是数据存储子系统。 每个数据存储子系统包括多个控制单元，其附接多个数据存储设备，例如用于代表各种主机系统存储数据的直接存取存储设备（DASD）。 每个控制单元具有用于使用动态路径访问外围数据存储设备的单独的存储路径。 存储路径可以集群到功率集群中。 维护人员通过控制单元或外围数据存储设备上的维护面板激活子系统，以从子系统顶部的所有主机系统中请求重新配置子系统。 主机系统可以根据不同的标准来满足请求或拒绝它。 在批准重新配置的每个主机系统中，子系统13被重新配置用于维护目的。 在完成维护过程之后，向主机系统发送第二重新配置请求，以使静止设备恢复正常操作。

    Performance enhancement system and method for a hierarchical data cache using a RAID parity scheme
    2.
    发明授权
    Performance enhancement system and method for a hierarchical data cache using a RAID parity scheme 失效
    使用RAID奇偶校验方案的分级数据高速缓存的性能增强系统和方法

    公开(公告)号：US5636359A

    公开(公告)日：1997-06-03

    申请号：US262208

    申请日：1994-06-20

    申请人： Brent C. Beardsley ,  Joel H. Cord ,  Joseph S. Hyde, II ,  Vernon J. Legvold ,  Carol S. Michod ,  Gary E. Morain ,  Chan Y. Ng ,  John R. Paveza ,  Lloyd R. Shipman, Jr.

    发明人： Brent C. Beardsley ,  Joel H. Cord ,  Joseph S. Hyde, II ,  Vernon J. Legvold ,  Carol S. Michod ,  Gary E. Morain ,  Chan Y. Ng ,  John R. Paveza ,  Lloyd R. Shipman, Jr.

    IPC分类号： G06F11/10 ,  G06F12/08

    CPC分类号： G06F12/0866 ,  G06F11/1008 ,  G06F12/0804

    摘要： A system and method for reducing device wait time in response to a host initiated write operation modifying a data block. The system includes a host computer channel connected to a storage controller which has cache memory and a nonvolatile storage buffer in a first embodiment. An identical system makes up the second embodiment with the exception that there is no nonvolatile storage buffer in the storage controller of the second embodiment. The controller in either embodiment is coupled to a cache storage drawer containing a plurality of DASD devices for implementing a RAID parity data protection scheme, and for permanently storing data. The drawer has nonvolatile cache memory which is used for accepting data destaged from controller cache. In a first embodiment, no commit reply is sent to the controller to indicate that data has been written to DASD. Instead a status information block is created to indicate that the data has been destaged from controller cache but is not committed. The status information is stored in directory means attached to the controller. The system uses this information to create a list of data which is in the state of Not committed. In this way data can be committed according to a cache management algorithm of least recently used (LRU), rather than requiring synchronous commit which is inefficient because it requires waiting on a commit response and ties up nonvolatile storage space allocated to back-up copies of cache data. In a second embodiment, directory means attached to the controller stores information about status blocks that may be modified or unmodified. The status information is used to eliminate wait times associated with waiting for data to be written to HDAs below.

    摘要翻译： 一种用于响应于修改数据块的主机发起的写操作来减少设备等待时间的系统和方法。 该系统包括在第一实施例中连接到具有高速缓冲存储器和非易失性存储缓冲器的存储控制器的主机通道。 除了在第二实施例的存储控制器中没有非易失性存储缓冲器之外，相同的系统构成第二实施例。 任一实施例中的控制器耦合到包含多个DASD设备的高速缓存存储抽屉，用于实现RAID奇偶校验数据保护方案，并用于永久存储数据。 抽屉具有非易失性高速缓存，用于接受从控制器高速缓存中分配的数据。 在第一实施例中，没有向控制器发送提交答复以指示数据已被写入DASD。 相反，创建状态信息块以指示数据已经从控制器高速缓存中取消但未提交。 状态信息存储在连接到控制器的目录中。 系统使用此信息创建处于未提交状态的数据列表。 以这种方式，可以根据最近最少使用的缓存管理算法（LRU）来提交数据，而不是要求同步提交是低效的，因为它需要等待提交响应并绑定分配给备份副本的非易失性存储空间 缓存数据。 在第二实施例中，连接到控制器的目录装置存储关于可以被修改或未修改的状态块的信息。 状态信息用于消除与等待数据写入下面的HDA相关联的等待时间。

    Systems and methods for background destaging storage tracks
    3.
    发明授权
    Systems and methods for background destaging storage tracks 失效
    后台存储轨道的系统和方法

    公开(公告)号：US08656109B2

    公开(公告)日：2014-02-18

    申请号：US12965141

    申请日：2010-12-10

    申请人： Brent C. Beardsley ,  Michael T. Benhase ,  Binny S. Gill ,  Lokesh M. Gupta ,  Sonny E. Williams

    发明人： Brent C. Beardsley ,  Michael T. Benhase ,  Binny S. Gill ,  Lokesh M. Gupta ,  Sonny E. Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0891 ,  G06F12/0804 ,  G06F12/0831 ,  G06F12/0848 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/12 ,  G06F12/128 ,  G06F2212/1041 ,  G06F2212/282 ,  G06F2212/313 ,  G06F2212/314 ,  G06F2212/604 ,  G06F2212/621

    摘要： A system includes a write cache configured to store a plurality of storage tracks and configured to be coupled to one or more hosts, and a processor coupled to the write cache. The processor includes code that, when executed by the processor, causes the processor to perform the method below. One method includes monitoring the write cache for write operations from the host(s) and determining if the host(s) is/are idle based on monitoring the write cache for write operations from the host(s). The storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle. Also provided are physical computer storage mediums including a computer program product for performing the above method.

    摘要翻译： 一种系统包括配置成存储多个存储轨道并被配置为耦合到一个或多个主机的写入高速缓存以及耦合到写入高速缓存的处理器。 处理器包括当由处理器执行时使处理器执行下面的方法的代码。 一种方法包括：监控来自主机的写入高速缓存，以及基于监视来自主机的写入操作的写入高速缓存来确定主机是否是空闲的。 如果主机是空闲的并且如果一个或多个主机不空闲，则不会从写高速缓存中将存储轨道从写高速缓存中移出。 还提供了包括用于执行上述方法的计算机程序产品的物理计算机存储介质。

    Intelligent write caching for sequential tracks
    4.
    发明授权
    Intelligent write caching for sequential tracks 有权
    用于顺序轨道的智能写缓存

    公开(公告)号：US08443141B2

    公开(公告)日：2013-05-14

    申请号：US12894017

    申请日：2010-09-29

    申请人： Brent C. Beardsley ,  Michael T. Benhase ,  Lokesh M. Gupta ,  Joseph S. Hyde, II ,  Sonny E. Williams

    发明人： Brent C. Beardsley ,  Michael T. Benhase ,  Lokesh M. Gupta ,  Joseph S. Hyde, II ,  Sonny E. Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/126 ,  G06F12/0804 ,  G06F12/0868

    摘要： Write caching for sequential tracks is performed by a processor device in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit. If a first track is determined to be sequential, and an earlier track is also determined to be sequential, a temporal bit associated with the earlier track is cleared to allow for destage of data of the earlier track. If a temporal bit for one of a plurality of additional tracks in one of a plurality of strides in a modified cache is determined to be not set, a stride associated with the one of the plurality of additional tracks is selected for a destage operation. If the NVS exceeds a predetermined storage threshold, a predetermined one of the plurality of strides is selected for the destage operation.

    摘要翻译： 用于顺序轨道的写缓存由用于将数据从非易失性存储（NVS）降级到存储单元的计算存储环境中的处理器设备执行。 如果确定第一轨道是顺序的，并且较早的轨道也被确定为顺序的，则与较早轨道相关联的时间位被清除以允许对先前轨道的数据进行排水。 如果确定修改的高速缓存中的多个步幅之一中的多个附加轨道之一的时间位未被设置，则选择与所述多个附加轨道中的一个相关联的步幅用于码头操作。 如果NVS超过预定的存储阈值，则选择多个步骤中的预定的一个步骤用于排水操作。

    System for increasing the efficiency of communications between controller and plurality of host computers by prohibiting retransmission of the same message for predetermined period of time
    7.
    发明授权
    System for increasing the efficiency of communications between controller and plurality of host computers by prohibiting retransmission of the same message for predetermined period of time 失效
    用于通过禁止在预定时间段内重传相同消息来提高控制器与多台主机之间的通信效率的系统

    公开(公告)号：US5461720A

    公开(公告)日：1995-10-24

    申请号：US949671

    申请日：1992-09-23

    申请人： Brent C. Beardsley ,  Adalberto G. Yanes

    发明人： Brent C. Beardsley ,  Adalberto G. Yanes

    IPC分类号： G06F13/16 ,  G06F15/02

    CPC分类号： G06F13/161

    摘要： A method and system for enhancing the efficiency of communication between multiple host computers and a storage system controller via multiple communication channels. After detecting a transmission of a specific message from the storage system controller to a selected host computer, channel data bits corresponding to that particular communication channel are set within preliminary control words which are stored in temporary storage locations. A timer circuit is coupled to the temporary storage locations and periodically resets the channel data bits. A final control word is then calculated by combining the channel data bits from all of the preliminary control words. A control circuit is then utilized to prohibit the retransmission of the specific message from the storage system controller to the selected host computer for a predetermined minimum period of time in response to the state of the channel data bits within the final control word. Communication efficiency is increased by eliminating unnecessary transmissions of a specific message.

    摘要翻译： 一种用于通过多个通信信道增强多个主机与存储系统控制器之间的通信效率的方法和系统。 在检测到来自存储系统控制器的特定消息到所选择的主计算机的传输之后，将对应于该特定通信信道的通道数据位设置在存储在临时存储位置的初步控制字中。 定时器电路耦合到临时存储位置，并周期性地复位通道数据位。 然后通过组合来自所有初步控制字的通道数据位来计算最终控制字。 然后，响应于最终控制字内的通道数据位的状态，控制电路用于禁止将特定消息从存储系统控制器重传到所选择的主计算机预定的最小时间段。 通过消除特定消息的不必要的传输来增加通信效率。

    Systems and methods for managing destage conflicts
    9.
    发明授权
    Systems and methods for managing destage conflicts 有权
    管理流离失所冲突的制度和方法

    公开(公告)号：US08661201B2

    公开(公告)日：2014-02-25

    申请号：US12965133

    申请日：2010-12-10

    申请人： Brent C. Beardsley ,  Michael T. Benhase ,  Binny S. Gill ,  Lokesh M. Gupta ,  Sonny E. Williams

    发明人： Brent C. Beardsley ,  Michael T. Benhase ,  Binny S. Gill ,  Lokesh M. Gupta ,  Sonny E. Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0891 ,  G06F12/023 ,  G06F12/0804 ,  G06F12/0866

    摘要： A system includes a cache partitioned into multiple ranks configured to store multiple storage tracks and a processor coupled to the cache. The processor is configured to perform the following method. One method includes allocating an amount of storage space in the cache to each rank and monitoring a current amount of storage space used by each rank with respect to the amount of storage space allocated to each respective rank. The method further includes destaging storage tracks from each rank until the current amount of storage space used by each respective rank is equal to a predetermined minimum amount of storage space with respect to the amount of storage space allocated to each rank. Also provided are physical computer storage mediums including code that, when executed by a processor, cause the processor to perform the above method.

    摘要翻译： 系统包括被分配成多个级别的缓存，其被配置为存储多个存储轨道，以及耦合到高速缓存的处理器。 处理器配置为执行以下方法。 一种方法包括将高速缓存中的存储空间量分配给每个等级，并且针对分配给每个相应等级的存储空间量来监视每个等级使用的当前存储空间量。 该方法还包括对每个等级的存储轨道进行降级，直到每个相应等级使用的当前存储空间量相对于分配给每个等级的存储空间量等于预定的最小存储空间量。 还提供了物理计算机存储介质，其包括当由处理器执行时使处理器执行上述方法的代码。

    Systems and methods for managing destage conflicts
    10.
    发明授权
    Systems and methods for managing destage conflicts 失效
    管理流离失所冲突的制度和方法

    公开(公告)号：US08595433B2

    公开(公告)日：2013-11-26

    申请号：US13493794

    申请日：2012-06-11

    申请人： Brent C. Beardsley ,  Michael T. Benhase ,  Binny S. Gill ,  Lokesh M. Gupta ,  Sonny E. Williams

    发明人： Brent C. Beardsley ,  Michael T. Benhase ,  Binny S. Gill ,  Lokesh M. Gupta ,  Sonny E. Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0891 ,  G06F12/023 ,  G06F12/0804 ,  G06F12/0866

    摘要： A system includes a cache partitioned into multiple ranks configured to store multiple storage tracks and a processor coupled to the cache. The processor is configured to perform the following method. One method includes allocating an amount of storage space in the cache to each rank and monitoring a current amount of storage space used by each rank with respect to the amount of storage space allocated to each respective rank. The method further includes destaging storage tracks from each rank until the current amount of storage space used by each respective rank is equal to a predetermined minimum amount of storage space with respect to the amount of storage space allocated to each rank.

    摘要翻译： 系统包括被分配成多个级别的缓存，其被配置为存储多个存储轨道，以及耦合到高速缓存的处理器。 处理器配置为执行以下方法。 一种方法包括将高速缓存中的存储空间量分配给每个等级，并且针对分配给每个相应等级的存储空间量来监视每个等级使用的当前存储空间量。 该方法还包括对每个等级的存储轨道进行降级，直到每个相应等级使用的当前存储空间量相对于分配给每个等级的存储空间量等于预定的最小存储空间量。