公开(公告)号：US06535937B1

公开(公告)日：2003-03-18

申请号：US09503911

申请日：2000-02-15

申请人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Russell Lee Ellison ,  Gregg Steven Lucas ,  Juan Antonio Yanes

发明人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Russell Lee Ellison ,  Gregg Steven Lucas ,  Juan Antonio Yanes

IPC分类号： G06F1338

CPC分类号： G06F13/4221 ,  G06F13/4027

摘要： A method and system to verify the passage of one or more write commands sent from an originating location through a PCI bus system. An addressable data storage is located substantially at the end of the PCI bus system with respect to the originating location. A write command is sent by the originator subsequent to the one or more write commands, to a predetermined special end location address identifying the addressable storage. The command is accompanied by data comprising a predetermined special return address at the originating location. The PCI bus system transmits the write commands on a FIFO basis, so the one or more write commands precede the subsequently sent write command. Logic senses the subsequently sent write command, and responds to the command, sending a return echo write command to the predetermined special return address. The returning echo write command verifies the passage of the write commands and data through the PCI bus system. The predetermined special end location address is the key to identify the subsequently sent write command.

摘要翻译： 一种用于验证从始发位置通过PCI总线系统发送的一个或多个写入命令的通过的方法和系统。 相对于始发位置，可寻址数据存储器基本上位于PCI总线系统的末端。 写命令由发起者在一个或多个写入命令之后发送到标识可寻址存储器的预定特殊结束位置地址。 该命令伴随着在始发位置处包括预定的特殊返回地址的数据。 PCI总线系统以FIFO为基础发送写命令，因此一个或多个写命令先于随后发送的写命令。 逻辑检测随后发送的写入命令，并响应该命令，向预定的特殊返回地址发送返回回显写命令。 返回的回写写命令通过PCI总线系统验证写命令和数据的通过。 预定的特殊终端位置地址是识别随后发送的写命令的关键。

公开(公告)号：US06530043B1

公开(公告)日：2003-03-04

申请号：US09522440

申请日：2000-03-09

申请人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Gregg Steven Lucas ,  Juan Antonio Yanes

发明人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Gregg Steven Lucas ,  Juan Antonio Yanes

IPC分类号： G06F1108

CPC分类号： H04L1/0061 ,  H04L1/0041 ,  H04L1/0045

摘要： In a PCI bus system, a method and system check for errors in rite data transferred from a PCI data source across a PCI bus to the PCI bus system, the data comprising a plurality of blocks. Redundancy calculation logic receives the write data across the PCI bus, calculates a check value for each block of the data transferred across the PCI bus, and updating any previously calculated check value with the calculated check value at a storage location of a storage memory. Data path logic is coupled to the PCI bus and to the storage memory, and responds to a unique identifier of a redundancy write command sent subsequent to completion of the transfer of the write data across the PCI interface. The data path logic responds to the write command unique identifier, detecting the updated calculated check value at the storage location of the storage memory. Error check logic coupled to the data path logic determines whether the detected updated calculated check value indicates an error, and upon the detected updated calculated check value indicating an error, signals the error.

摘要翻译： 在PCI总线系统中，方法和系统检查从PCI数据源通过PCI总线传输到PCI总线系统的仪表数据中的错误，该数据包括多个块。 冗余计算逻辑通过PCI总线接收写入数据，计算通过PCI总线传输的数据的每个块的校验值，并且在存储存储器的存储位置处用计算出的校验值更新任何先前计算的校验值。 数据路径逻辑耦合到PCI总线和存储存储器，并且响应在完成跨PCI接口的写入数据传送之后发送的冗余写入命令的唯一标识符。 数据路径逻辑响应写入命令唯一标识符，检测在存储存储器的存储位置处更新的计算的检查值。 耦合到数据路径逻辑的错误检查逻辑确定检测到的更新的计算的检查值是否指示错误，并且在检测到的更新的指示错误的计算的检查值时，发信号通知错误。

公开(公告)号：US06189117B1

公开(公告)日：2001-02-13

申请号：US09135835

申请日：1998-08-18

申请人： Gary William Batchelor ,  Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Jack Harvey Derenburger ,  Carl Evan Jones ,  Robert Earl Medlin ,  Belayneh Tafesse ,  Juan Antonio Yanes

发明人： Gary William Batchelor ,  Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Jack Harvey Derenburger ,  Carl Evan Jones ,  Robert Earl Medlin ,  Belayneh Tafesse ,  Juan Antonio Yanes

IPC分类号： G06F1100

CPC分类号： G06F11/0796

摘要： Disclosed is a system for handling errors. A system managed by a processor processes an error in the system. The system then generates an interrupt to the processor indicating that an error occurred and executes an error mode before the processor interprets the interrupt. As part of the error mode, the system prevents data from transferring between the system and the processor and processes a read request from the processor to the system by returning data to the processor unrelated to the requested data. The processor would then process the interrupt indicating the error and execute a diagnostic mode to diagnose the error in the system.

摘要翻译： 公开了一种处理错误的系统。 由处理器管理的系统处理系统中的错误。 系统然后在处理器解释中断之前，向处理器产生指示发生错误的中断并执行错误模式。 作为错误模式的一部分，系统防止数据在系统和处理器之间传输，并通过将数据返回到与请求的数据无关的处理器来处理从处理器到系统的读取请求。 然后处理器将处理指示错误的中断，并执行诊断模式以诊断系统中的错误。

公开(公告)号：US06785771B2

公开(公告)日：2004-08-31

申请号：US10005003

申请日：2001-12-04

申请人： Kevin John Ash ,  Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Joseph Smith Hyde, II ,  Thomas Charles Jarvis ,  Steven Robert Lowe ,  David Frank Mannenbach

发明人： Kevin John Ash ,  Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Joseph Smith Hyde, II ,  Thomas Charles Jarvis ,  Steven Robert Lowe ,  David Frank Mannenbach

IPC分类号： G06F1200

CPC分类号： G06F12/0871 ,  G06F12/0804

摘要： Provided is a method, system, and program for destaging data from a first computer readable medium to a second computer readable medium. A list of entries indicating data blocks in the first computer readable medium is scanned. For each entry scanned, a determination is made as to whether the data block indicated in the scanned entry satisfies a criteria. If the data block indicated in the scanned entry satisfies the criteria, then a destage operation is called to destage the data block in the scanned entry from the first computer readable medium to the second computer readable medium. If the called destage operation is not initiated, then the scanned entry is removed from the cache list. The removed scanned entry is added to one destage wait list. During one destage operation, data blocks indicated in entries in the destage wait list are destaged.

摘要翻译： 提供了一种用于将数据从第一计算机可读介质降级到第二计算机可读介质的方法，系统和程序。 扫描第一计算机可读介质中指示数据块的条目列表。 对于扫描的每个条目，确定扫描条目中指示的数据块是否满足标准。 如果扫描条目中指示的数据块满足标准，则调度一个转移操作以将扫描条目中的数据块从第一计算机可读介质转移到第二计算机可读介质。 如果未启动所呼叫的终止操作，则从缓存列表中删除扫描的条目。 已删除的扫描条目将添加到一个目的地等待列表中。 在一个运行期间，在目的地等待列表中的条目中指示的数据块已停止运行。

公开(公告)号：US06438661B1

公开(公告)日：2002-08-20

申请号：US09261824

申请日：1999-03-03

申请人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Douglas A. Martin ,  Robert Louis Morton ,  Kenneth Wayne Todd

发明人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Douglas A. Martin ,  Robert Louis Morton ,  Kenneth Wayne Todd

IPC分类号： G06F1206

CPC分类号： G06F11/1435 ,  Y10S707/99953

摘要： Disclosed is a method, system, and article of manufacture for processing modified meta data for data recovery operations. The meta data provides information on user data maintained in a storage device. The system determines whether meta data tracks maintained in a cache were modified and indicates in a non-volatile memory that the determined meta data tracks were modified. Data recovery operations may be initiated as a result of a system failure, such as a warmstart or coldstart recovery. During such data recovery operations, the system processes the non-volatile memory and the indications of modified meta data tracks therein to rebuild lost meta data tracks in the cache.

摘要翻译： 公开了用于处理用于数据恢复操作的修改的元数据的方法，系统和制品。 元数据提供有关存储设备中维护的用户数据的信息。 该系统确定在高速缓存中维护的元数据轨道是否被修改，并且在非易失性存储器中指示修改了所确定的元数据轨道。 数据恢复操作可能由于系统故障（如热启动或冷启动恢复）而启动。 在这种数据恢复操作期间，系统处理非易失性存储器及其中修改的元数据轨迹的指示，以重构高速缓存中的丢失的元数据轨道。

公开(公告)号：US06381677B1

公开(公告)日：2002-04-30

申请号：US09136626

申请日：1998-08-19

申请人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Joseph Smith Hyde ,  Thomas Charles Jarvis ,  Douglas A. Martin ,  Robert Louis Morton

发明人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Joseph Smith Hyde ,  Thomas Charles Jarvis ,  Douglas A. Martin ,  Robert Louis Morton

IPC分类号： G06F1212

CPC分类号： G06F12/0862 ,  G06F12/0866 ,  G06F2212/312

摘要： Disclosed is a system for caching data. After determining a sequential access of a first memory area, such as a direct access storage device (DASD), a processing unit stages a group of data sets from the first memory area to a second memory, such as cache. The processing unit processes a data access request (DAR) for data sets in the first memory area that are included in the sequential access and reads the requested data sets from the second memory area. The processing unit determines trigger data set from a plurality of trigger data sets based on a trigger data set criteria. The processing unit then stages a next group of data sets from the first memory area to the second memory area in response to reading the determined trigger data set.

摘要翻译： 公开了一种用于缓存数据的系统。 在确定诸如直接存取存储设备（DASD）之类的第一存储区域的顺序存取之后，处理单元将来自第一存储器区域的一组数据集合到诸如高速缓存的第二存储器。 处理单元处理包括在顺序访问中的第一存储器区域中的数据集的数据访问请求（DAR），并从第二存储器区域读取所请求的数据集。 处理单元基于触发数据集标准从多个触发数据集确定触发数据集。 响应于读取所确定的触发数据集，处理单元将下一组数据集从第一存储器区域转移到第二存储区域。

公开(公告)号：US5893918A

公开(公告)日：1999-04-13

申请号：US885099

申请日：1992-05-18

申请人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Susan Marie Wethington

发明人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Susan Marie Wethington

IPC分类号： G06F13/10 ,  G06F3/06 ,  G06F12/08 ,  G06F13/14 ,  G06F13/00

CPC分类号： G06F3/0601 ,  G06F12/0866 ,  G06F2003/0692

摘要： A method for operating a controller for a plurality of direct access storage devices to minimize rotational misses during data transfer operations. Transferred data is staged into a controller cache when a rotational position sensing miss avoidance reconnection is made. Circumstances are detailed for qualifying an operation pending on direct access storage devices for treatment as miss avoidance candidates. Adjustment of controller response depending upon foreknowledge that a channel command word chain includes a write operation is also accomplished utilizing the present method.

摘要翻译： 一种用于操作用于多个直接存取存储设备的控制器以最小化数据传送操作期间的转移错误的方法。 当进行旋转位置感测错过回避重新连接时，传送的数据被分段到控制器高速缓存中。 对于直接访问存储设备进行等待处理的错误回避候选人的操作，情况是详细的。 使用本方法也可以根据预先知道通道命令字链包括写入操作来调整控制器响应。

公开(公告)号：US06658542B2

公开(公告)日：2003-12-02

申请号：US10293508

申请日：2002-11-13

申请人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Robert Louis Morton ,  Kenneth Wayne Todd

发明人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Robert Louis Morton ,  Kenneth Wayne Todd

IPC分类号： G06F1202

CPC分类号： G06F11/073 ,  G06F11/004 ,  G06F11/0724 ,  G06F11/0727 ,  G06F11/0793 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/312

摘要： Disclosed is a system and method for caching data. A processor receives data from a host to modify a track in a first storage device. The processor stores a copy of the modified data in a cache and indicates in a second storage device the tracks for which there is modified data in cache. During data recovery operations, the processor processes the second storage device and data therein to determine the tracks for which there was modified data in cache. The processor then marks the determined tracks as failed to prevent data at the determined tracks in the first storage device from being returned in response to a read request until the failure is resolved. In further embodiments, in response to detecting a partial failure within the storage system, the processor would scan the cache to determine tracks for which there is modified data stored in the cache. The processor then stores in the second storage device information indicating the tracks having modified data in cache and schedules the destaging of the modified data from the cache to the first storage device. The processor is further capable of receiving and processing read/write requests directed to the first storage device before all the modified data is destaged from cache.

摘要翻译： 公开了一种用于缓存数据的系统和方法。 处理器从主机接收数据以修改第一存储设备中的轨道。 处理器将修改的数据的副本存储在高速缓存中，并且在第二存储设备中指示在高速缓存中有修改数据的轨道。 在数据恢复操作期间，处理器处理第二存储设备及其中的数据以确定高速缓存中已修改数据的轨道。 然后，处理器将确定的轨道标记为失败，以防止响应于读取请求而返回第一存储设备中确定的轨道上的数据，直到故障被解决为止。 在另外的实施例中，响应于检测存储系统中的部分故障，处理器将扫描高速缓存以确定存储在高速缓存中的修改数据的轨道。 然后，处理器在第二存储设备中存储指示在高速缓存中具有修改数据的轨道的信息，并且将修改后的数据从高速缓存调度到第一存储设备。 在所有修改的数据从缓存中移出之前，处理器还能够接收和处理指向第一存储设备的读/写请求。

公开(公告)号：US06327644B1

公开(公告)日：2001-12-04

申请号：US09135842

申请日：1998-08-18

申请人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Douglas A. Martin ,  Robert Louis Morton ,  Mark A. Reid

发明人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Douglas A. Martin ,  Robert Louis Morton ,  Mark A. Reid

IPC分类号： G06F1208

CPC分类号： G06F12/123

摘要： Disclosed is a system for managing data in cache. A list of data entries in a first memory area has a first end and a second end, such as a most recently used (MRU) end and least recently used (LRU) end. A first pointer addresses a data entry in the list and a second pointer addresses another data entry in the list that is not at the first and second ends. Data from a second memory area is provided to add to the list. A determination is made as to whether the provided data to add to the list is one of a first type and second type of data, such as sequentially accessed data or non-sequentially accessed data. The provided data is stored in the first memory area as a new data entry in the list. The first pointer is modified to address the new data entry after determining that the provided data is of the first type. After determining that the provided data is of the second type, the second pointer is processed to determine where to add the new data entry to the list between the first and second ends.

摘要翻译： 公开了一种用于管理缓存中的数据的系统。 第一存储器区域中的数据条目的列表具有第一端和第二端，诸如最近使用（MRU）端和最近最少使用（LRU）端。 第一个指针寻址列表中的数据条目，第二个指针寻址列表中不在第一和第二端的另一个数据条目。 来自第二存储器区域的数据被提供以添加到列表中。 确定添加到列表中的所提供的数据是否是第一类型和第二类型的数据之一，诸如顺序访问的数据或非顺序访问的数据。 所提供的数据作为列表中的新数据条目存储在第一存储器区域中。 在确定所提供的数据是第一类型之后，修改第一个指针以解决新的数据条目。 在确定所提供的数据是第二类型之后，处理第二指针以确定在第一和第二端之间将新数据条目添加到列表的哪里。

公开(公告)号：US6035347A

公开(公告)日：2000-03-07

申请号：US994312

申请日：1997-12-19

申请人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Forrest Lee Wade

发明人： Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Forrest Lee Wade

IPC分类号： G06F11/14 ,  C06F11/10

CPC分类号： G06F11/1441

摘要： A data storage system and method for securely storing data includes (a) a host CPU; (b) a non-volatile storage (NVS) memory for storing data; (c) a processor, the processor being coupled to the host CPU and the NVS memory and monitoring availability of space in the NVS memory and in a non-volatile buffer (NV-Buffer); and (d) the NV-Buffer, the NV-Buffer being coupled to the host CPU, the NVS memory, and the processor, upon receiving a request to write data into the NVS memory, the host CPU storing data to be transferred to the NVS memory into the NV-Buffer, and upon receiving a confirmation message that data of a write operation to the NV-Buffer is committed, the NV-Buffer transferring the data to the NVS memory. The NVS memory includes a fast dump space for storing data transferred from the NV-Buffer when a main power is down and for restoring back data from the NVS memory to the NV-Buffer when the power is up. The NV-Buffer is a fast drain buffer and is equipped with a backup power source sufficient to hold up a power needed to transfer the data when the power is down.

摘要翻译： 用于安全地存储数据的数据存储系统和方法包括：（a）主机CPU; （b）用于存储数据的非易失性存储（NVS）存储器; （c）处理器，所述处理器耦合到所述主机CPU和所述NVS存储器并且监视所述NVS存储器和非易失性缓冲器（NV缓冲器）中的空间的可用性; 和（d）NV缓冲器，NV缓冲器在接收到将数据写入NVS存储器的请求时，耦合到主机CPU，NVS存储器和处理器，主机CPU存储要传送到 NVS存储器进入NV-Buffer，并且在接收到对NV-Buffer的写入操作的数据提交的确认消息时，NV-Buffer将数据传送到NVS存储器。 NVS存储器包括快速转储空间，用于在主电源关闭时存储从NV-Buffer传输的数据，并在电源关闭时将数据从NVS存储器恢复到NV缓冲区。 NV-Buffer是一个快速漏极缓冲器，并配有备用电源，足以在掉电时保持传输数据所需的电力。