摘要:
Computer systems with direct updating of cache (e.g., primary L1 cache) memories of a processor, such as a central processing unit (CPU) or graphics processing unit (GPU). Special addresses are reserved for high speed memory. Memory access requests involving these reserved addresses are routed directly to the high speed memory. Memory access requests not involving these reserved addresses are routed to memory external to the processor.
摘要:
Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels may be utilized to conduct request/response transactions between the remote device and processor that satisfy a set of associated coherency rules.
摘要:
According to embodiments of the invention, separate spatial indexes may be created which correspond to dynamic objects in a three dimensional scene and static objects in the three dimensional scene. By creating separate spatial indexes for static and dynamic objects, only the dynamic spatial index may need to be rebuilt in response to movement or changes in shape of objects in the three dimensional scene. Furthermore, the static and dynamic spatial indexes may be stored in separate portions of an image processing system's memory cache. By storing the static spatial index and the dynamic spatial index in separate portions of the memory cache, the dynamic portion of the memory cache may be updated without affecting the static portion of the spatial index in the memory cache.
摘要:
Graphics rendering on a network on chip (‘NOC’) including receiving, in the geometry processor, a representation of an object to be rendered; converting, by the geometry processor, the representation of the object to two dimensional primitives; sending, by the geometry processor, the primitives to the plurality of scan converters; converting, by the scan converters, the primitives to fragments, each fragment comprising one or more portions of a pixel; for each fragment: selecting, by the scan converter for the fragment in dependence upon sorting rules, a pixel processor to process the fragment; sending, by the scan converter to the pixel processor, the fragment; and processing, by the pixel processor, the fragment to produce pixels for an image.
摘要:
Graphics rendering on a network on chip (‘NOC’) including receiving, in the geometry processor, a representation of an object to be rendered; converting, by the geometry processor, the representation of the object to two dimensional primitives; sending, by the geometry processor, the primitives to the plurality of scan converters; converting, by the scan converters, the primitives to fragments, each fragment comprising one or more portions of a pixel; for each fragment: selecting, by the scan converter for the fragment in dependence upon sorting rules, a pixel processor to process the fragment; sending, by the scan converter to the pixel processor, the fragment; and processing, by the pixel processor, the fragment to produce pixels for an image.
摘要:
According to embodiments of the invention, separate spatial indexes may be created which correspond to dynamic objects in a three dimensional scene and static objects in the three dimensional scene. By creating separate spatial indexes for static and dynamic objects, only the dynamic spatial index may need to be rebuilt in response to movement or changes in shape of objects in the three dimensional scene. Furthermore, the static and dynamic spatial indexes may be stored in separate portions of an image processing system's memory cache. By storing the static spatial index and the dynamic spatial index in separate portions of the memory cache, the dynamic portion of the memory cache may be updated without affecting the static portion of the spatial index in the memory cache.
摘要:
Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, each network interface controller controlling inter-IP block communications through routers, with each IP block also adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.
摘要:
Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, each network interface controller controlling inter-IP block communications through routers, with each IP block also adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.
摘要:
A network on chip (‘NOC’) comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block coupled to a router through a memory communications controller and a network interface controller, the NOC also including a port on a router of the network through which is received an invalidate command, the invalidate command including an identification of a cache line, the invalidate command representing an instruction to invalidate the cache line, the router configured to send the invalidate command to an IP block served by the router; the router further configured to send the invalidate command horizontally and vertically to neighboring routers if the port is a vertical port; and the router further configured to send the invalidate command only horizontally to neighboring routers if the port is a horizontal port.
摘要:
A network on chip (‘NOC’) that maintains cache coherency with invalidate commands, the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, the NOC also including a port on a router of the network through which is received an invalidate command, the invalidate command including an identification of a cache line, the invalidate command representing an instruction to invalidate the cache line, the router configured to send the invalidate command to an IP block served by the router; the router further configured to send the invalidate command horizontally and vertically to neighboring routers if the port is a vertical port; and the router further configured to send the invalidate command only horizontally to neighboring routers if the port is a horizontal port.