公开(公告)号：US07273789B2

公开(公告)日：2007-09-25

申请号：US11227503

申请日：2005-09-15

申请人： Byoung Gue Min ,  Jong Min Lee ,  Seong Il Kim ,  Chul Won Ju ,  Kyung Ho Lee

发明人： Byoung Gue Min ,  Jong Min Lee ,  Seong Il Kim ,  Chul Won Ju ,  Kyung Ho Lee

IPC分类号： H01L21/331

CPC分类号： H01L29/66318 ,  H01L29/7371

摘要： Provided is a method of fabricating a heterojunction bipolar transistor (HBT). The method includes: sequentially depositing a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter capping layer on a substrate; forming an emitter electrode on the emitter capping layer; forming a mesa type emitter to expose the base layer by sequentially etching the emitter capping layer and the emitter layer using the emitter electrode as an etch mask in vertical and negative-sloped directions to the substrate, respectively; and forming a base electrode on the exposed base layer using the emitter electrode as a mask in self-alignment with the emitter electrode. In this method, a distance between the mesa type emitter and the base electrode can be minimized and reproducibly controlled. Also, a self-aligned device with an excellent high-frequency characteristic can be embodied.

摘要翻译： 提供了一种制造异质结双极晶体管（HBT）的方法。 该方法包括：在衬底上依次沉积副集电极层，集电极层，基极层，发射极层和发射极覆盖层; 在发射极盖层上形成发射电极; 通过使用发射极电极作为蚀刻掩模，分别在垂直和负向倾斜的方向上依次蚀刻发射极覆盖层和发射极层来形成台面型发射极以暴露基底层; 以及使用发射电极作为与发射极电极自对准的掩模，在所述暴露的基底层上形成基极。 在这种方法中，台面型发射极和基极之间的距离可以被最小化并可重复地控制。 此外，可以实现具有优异的高频特性的自对准装置。

公开(公告)号：US07494909B2

公开(公告)日：2009-02-24

申请号：US11499116

申请日：2006-08-03

申请人： Chull Won Ju ,  Byoung Gue Min ,  Seong Il Kim ,  Jong Min Lee ,  Kyung Ho Lee ,  Young Il Kang

发明人： Chull Won Ju ,  Byoung Gue Min ,  Seong Il Kim ,  Jong Min Lee ,  Kyung Ho Lee ,  Young Il Kang

IPC分类号： H01L21/00 ,  H01L21/76 ,  H01L21/46 ,  H01L21/44 ,  H01L29/40 ,  H01L23/02

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

摘要： Provided are a chip, a chip stack, and a method of manufacturing the same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in a via hole exposing the bottom of the pad are stacked such that the pad and the metal layer of adjacent chips are bonded. This leads to a simplified manufacturing process, high chip performance and a small footprint for a chip stack.

摘要翻译： 提供一种芯片，芯片堆叠及其制造方法。 多个芯片，每个芯片包括：形成在晶片上的至少一个焊盘; 并且从晶片的底部突出到预定厚度并且形成在露出焊盘底部的通孔中的金属层被堆叠成使得焊盘和相邻芯片的金属层接合。 这导致了简化的制造工艺，高芯片性能和用于芯片堆叠的小占地面积。

公开(公告)号：US20090140439A1

公开(公告)日：2009-06-04

申请号：US12364475

申请日：2009-02-02

申请人： Chull Won Ju ,  Byoung Gue Min ,  Seong II Kim ,  Jong Min Lee ,  Kyung Ho Lee ,  Young II Kang

发明人： Chull Won Ju ,  Byoung Gue Min ,  Seong II Kim ,  Jong Min Lee ,  Kyung Ho Lee ,  Young II Kang

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

摘要： Provided are a chip, a chip stack, and a method of manufacturing the Same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in a via hole exposing the bottom of the pad are stacked such that the pad and the metal layer of adjacent chips are bonded. This leads to a simplified manufacturing process, high chip performance and a small footprint for a chip stack.

摘要翻译： 提供了芯片，芯片堆叠以及制造该芯片的方法。 多个芯片，每个芯片包括：形成在晶片上的至少一个焊盘; 并且从晶片的底部突出到预定厚度并且形成在露出焊盘底部的通孔中的金属层被堆叠成使得焊盘和相邻芯片的金属层接合。 这导致了简化的制造工艺，高芯片性能和用于芯片堆叠的小占地面积。

公开(公告)号：US09977071B2

公开(公告)日：2018-05-22

申请号：US14302354

申请日：2014-06-11

申请人： Jong Min Lee ,  Chull Won Ju ,  Byoung Gue Min

发明人： Jong Min Lee ,  Chull Won Ju ,  Byoung Gue Min

IPC分类号： G01R31/26

CPC分类号： G01R31/2621 ,  G01R31/2608

摘要： A test device includes: a testing unit connected with a measurement line, and configured to apply bias to the measurement line and measure the measurement line; a plurality of switching units configured to electrically connect the measurement line and the plurality of samples; and a control unit configured to sequentially turn on the plurality of switching units to sequentially apply the bias to the plurality of samples. The control unit determines whether a corresponding device sample has a defect based on a first measurement value according to measurement by the testing unit when the bias is applied to each of the plurality of samples.