公开(公告)号：US20080237685A1

公开(公告)日：2008-10-02

申请号：US11822548

申请日：2007-07-06

申请人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

发明人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.

摘要翻译： 在一个实施例中，半导体存储器件包括具有突出部分的半导体衬底，在至少一个突出半导体衬底部分上形成的隧道绝缘层，以及设置在隧道绝缘层上的浮动栅极结构。 浮动栅极结构的上部比浮动栅极结构的下部宽，并且浮动栅极结构的下部具有小于隧道绝缘层的宽度的宽度。 第一绝缘层部分形成在半导体衬底中并从半导体衬底突出，使得浮栅结构设置在突出的第一绝缘层部分之间。 在第一绝缘层部分和浮动栅极结构之上形成电介质层，并且在电介质层上形成控制栅极。

公开(公告)号：US08809932B2

公开(公告)日：2014-08-19

申请号：US11822548

申请日：2007-07-06

申请人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

发明人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.

摘要翻译： 在一个实施例中，半导体存储器件包括具有突出部分的半导体衬底，在至少一个突出半导体衬底部分上形成的隧道绝缘层，以及设置在隧道绝缘层上的浮动栅极结构。 浮动栅极结构的上部比浮动栅极结构的下部宽，并且浮动栅极结构的下部具有小于隧道绝缘层的宽度的宽度。 第一绝缘层部分形成在半导体衬底中并从半导体衬底突出，使得浮栅结构设置在突出的第一绝缘层部分之间。 在第一绝缘层部分和浮动栅极结构之上形成电介质层，并且在电介质层上形成控制栅极。

公开(公告)号：US08053347B2

公开(公告)日：2011-11-08

申请号：US12379190

申请日：2009-02-13

申请人： Hee-Soo Kang ,  Byung-Kyu Cho ,  Choong-Ho Lee ,  Dong-Uk Choi

发明人： Hee-Soo Kang ,  Byung-Kyu Cho ,  Choong-Ho Lee ,  Dong-Uk Choi

IPC分类号： H01L21/3205

CPC分类号： H01L21/28052 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66545

摘要： A method of manufacturing a semiconductor device, including forming a plurality of gate structures on a substrate, the gate structures each including a hard mask pattern stacked on a gate conductive pattern, forming an insulating layer pattern between the gate structures at least partially exposing a top surface of the hard mask pattern, forming a trench that exposes at least a top surface of the gate conductive pattern by selectively removing the hard mask pattern, and forming a silicide layer on the exposed gate conductive pattern.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成多个栅极结构，所述栅极结构各自包括堆叠在栅极导电图案上的硬掩模图案，在栅极结构之间形成至少部分地暴露顶部的绝缘层图案 形成通过选择性地去除硬掩模图案而暴露出栅极导电图案的至少顶表面的沟槽，以及在暴露的栅极导电图案上形成硅化物层的沟槽。

公开(公告)号：US07602005B2

公开(公告)日：2009-10-13

申请号：US11759044

申请日：2007-06-06

申请人： Byung-Kyu Cho ,  Tae-Yong Kim ,  Choong-Ho Lee

发明人： Byung-Kyu Cho ,  Tae-Yong Kim ,  Choong-Ho Lee

IPC分类号： H01L27/115

CPC分类号： H01L27/11568 ,  B82Y10/00 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531

摘要： A NOR flash memory device includes a substrate having trenches that extend in a first direction and stepped portions that are arranged between the trenches. A bit region having a linear shape extends in a second direction substantially perpendicular to the first direction in the substrate. The bit region is doped with impurities. A first dielectric layer is on the substrate having the trenches. An electric charge trap layer is on the first dielectric layer. A second dielectric layer is on the electric charge trap layer. An upper electrode is on sidewalls of the trenches. The upper electrode has a spacer shape. Related fabrication methods are also described.

摘要翻译： NOR闪存器件包括具有沿第一方向延伸的沟槽的衬底和布置在沟槽之间的台阶部分。 具有直线形状的位区域沿着基板中基本上垂直于第一方向的第二方向延伸。 该位区掺杂有杂质。 第一电介质层位于具有沟槽的衬底上。 电荷陷阱层位于第一介电层上。 第二介电层位于电荷陷阱层上。 上电极位于沟槽的侧壁上。 上电极具有间隔件形状。 还描述了相关的制造方法。

公开(公告)号：US20080001211A1

公开(公告)日：2008-01-03

申请号：US11759044

申请日：2007-06-06

申请人： Byung-Kyu Cho ,  Tae-Yong Kim ,  Choong-Ho Lee

发明人： Byung-Kyu Cho ,  Tae-Yong Kim ,  Choong-Ho Lee

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L27/11568 ,  B82Y10/00 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531

摘要： A NOR flash memory device includes a substrate having trenches that extend in a first direction and stepped portions that are arranged between the trenches. A bit region having a linear shape extends in a second direction substantially perpendicular to the first direction in the substrate. The bit region is doped with impurities. A first dielectric layer is on the substrate having the trenches. An electric charge trap layer is on the first dielectric layer. A second dielectric layer is on the electric charge trap layer. An upper electrode is on sidewalls of the trenches. The upper electrode has a spacer shape. Related fabrication methods are also described.

摘要翻译： NOR闪存器件包括具有沿第一方向延伸的沟槽的衬底和布置在沟槽之间的台阶部分。 具有直线形状的位区域沿着基板中基本上垂直于第一方向的第二方向延伸。 该位区掺杂有杂质。 第一电介质层位于具有沟槽的衬底上。 电荷陷阱层位于第一电介质层上。 第二介电层位于电荷陷阱层上。 上电极位于沟槽的侧壁上。 上电极具有间隔件形状。 还描述了相关的制造方法。

公开(公告)号：US09577115B2

公开(公告)日：2017-02-21

申请号：US13195347

申请日：2011-08-01

申请人： Byung-Kyu Cho ,  Chang-Hyun Lee ,  Young-Woo Park

发明人： Byung-Kyu Cho ,  Chang-Hyun Lee ,  Young-Woo Park

IPC分类号： H01L21/70 ,  H01L29/788 ,  H01L21/764 ,  H01L27/115 ,  H01L29/423

CPC分类号： H01L29/7881 ,  H01L21/764 ,  H01L27/11521 ,  H01L29/42336

摘要： A semiconductor device has an isolation layer pattern, a plurality of gate structures, and a first insulation layer pattern. The isolation layer pattern is formed on a substrate and has a recess thereon. The gate structures are spaced apart from each other on the substrate and the isolation layer pattern. The first insulation layer pattern is formed on the substrate and covers the gate structures and an inner wall of the recess. The first insulation layer pattern has a first air gap therein.

摘要翻译： 半导体器件具有隔离层图案，多个栅极结构和第一绝缘层图案。 隔离层图案形成在基板上并且在其上具有凹部。 栅极结构在衬底和隔离层图案上彼此间隔开。 第一绝缘层图案形成在基板上并且覆盖该凹槽的栅极结构和内壁。 第一绝缘层图案中具有第一气隙。