利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

191 条记录 (耗时 0.026 秒)

    Memory devices including spacer-shaped electrodes on pedestals and methods of manufacturing the same
    1.
    发明授权
    Memory devices including spacer-shaped electrodes on pedestals and methods of manufacturing the same 失效
    存储器件包括基座上的间隔电极及其制造方法

    公开(公告)号：US07602005B2

    公开(公告)日：2009-10-13

    申请号：US11759044

    申请日：2007-06-06

    申请人： Byung-Kyu Cho ,  Tae-Yong Kim ,  Choong-Ho Lee

    发明人： Byung-Kyu Cho ,  Tae-Yong Kim ,  Choong-Ho Lee

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11568 ,  B82Y10/00 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531

    摘要： A NOR flash memory device includes a substrate having trenches that extend in a first direction and stepped portions that are arranged between the trenches. A bit region having a linear shape extends in a second direction substantially perpendicular to the first direction in the substrate. The bit region is doped with impurities. A first dielectric layer is on the substrate having the trenches. An electric charge trap layer is on the first dielectric layer. A second dielectric layer is on the electric charge trap layer. An upper electrode is on sidewalls of the trenches. The upper electrode has a spacer shape. Related fabrication methods are also described.

    摘要翻译： NOR闪存器件包括具有沿第一方向延伸的沟槽的衬底和布置在沟槽之间的台阶部分。 具有直线形状的位区域沿着基板中基本上垂直于第一方向的第二方向延伸。 该位区掺杂有杂质。 第一电介质层位于具有沟槽的衬底上。 电荷陷阱层位于第一介电层上。 第二介电层位于电荷陷阱层上。 上电极位于沟槽的侧壁上。 上电极具有间隔件形状。 还描述了相关的制造方法。

    MEMORY DEVICES INCLUDING SPACER-SHAPED ELECTRODES ON PEDESTALS AND METHODS OF MANUFACTURING THE SAME
    2.
    发明申请
    MEMORY DEVICES INCLUDING SPACER-SHAPED ELECTRODES ON PEDESTALS AND METHODS OF MANUFACTURING THE SAME 失效
    包含间隔型电极的记忆装置及其制造方法

    公开(公告)号：US20080001211A1

    公开(公告)日：2008-01-03

    申请号：US11759044

    申请日：2007-06-06

    申请人： Byung-Kyu Cho ,  Tae-Yong Kim ,  Choong-Ho Lee

    发明人： Byung-Kyu Cho ,  Tae-Yong Kim ,  Choong-Ho Lee

    IPC分类号： H01L21/336 ,  H01L29/76

    CPC分类号： H01L27/11568 ,  B82Y10/00 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531

    摘要： A NOR flash memory device includes a substrate having trenches that extend in a first direction and stepped portions that are arranged between the trenches. A bit region having a linear shape extends in a second direction substantially perpendicular to the first direction in the substrate. The bit region is doped with impurities. A first dielectric layer is on the substrate having the trenches. An electric charge trap layer is on the first dielectric layer. A second dielectric layer is on the electric charge trap layer. An upper electrode is on sidewalls of the trenches. The upper electrode has a spacer shape. Related fabrication methods are also described.

    摘要翻译： NOR闪存器件包括具有沿第一方向延伸的沟槽的衬底和布置在沟槽之间的台阶部分。 具有直线形状的位区域沿着基板中基本上垂直于第一方向的第二方向延伸。 该位区掺杂有杂质。 第一电介质层位于具有沟槽的衬底上。 电荷陷阱层位于第一电介质层上。 第二介电层位于电荷陷阱层上。 上电极位于沟槽的侧壁上。 上电极具有间隔件形状。 还描述了相关的制造方法。

    Nonvolatile memory cells having high control gate coupling ratios using grooved floating gates and methods of forming same
    3.
    发明申请
    Nonvolatile memory cells having high control gate coupling ratios using grooved floating gates and methods of forming same 失效
    具有使用沟槽浮动栅极的高控制栅极耦合比的非易失性存储单元及其形成方法

    公开(公告)号：US20050260814A1

    公开(公告)日：2005-11-24

    申请号：US11121887

    申请日：2005-05-04

    申请人： Eun-Suk Cho ,  Choong-Ho Lee ,  Tae-Yong Kim

    发明人： Eun-Suk Cho ,  Choong-Ho Lee ,  Tae-Yong Kim

    IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/788

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/66787 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7881

    摘要： A non-volatile memory cell includes a semiconductor substrate having a fin-shaped active region extending therefrom. A tunnel dielectric layer is provided, which extends on opposing sidewalls and an upper surface of the fin-shaped active region. A floating gate electrode is provided on the tunnel dielectric layer. This floating gate electrode has at least a partial groove therein. An inter-gate dielectric layer is also provided. This inter-gate dielectric layer extends on the floating gate electrode and into the at least a partial groove. A control gate electrode is provided, which extends on the inter-gate dielectric layer and into the at least a partial groove.

    摘要翻译： 非易失性存储单元包括具有从其延伸的鳍状有源区的半导体衬底。 提供隧道电介质层，其在相对的侧壁上延伸并且在鳍状有源区域的上表面上延伸。 在隧道电介质层上设置浮栅电极。 该浮栅电极中至少有一部分凹槽。 还提供了栅极间电介质层。 该栅极间电介质层在浮栅电极上延伸并进入至少一部分槽。 提供控制栅极电极，其在栅极间电介质层上延伸并且进入至少部分凹槽。

    Non-volatile memory cells including fin structures
    6.
    发明授权
    Non-volatile memory cells including fin structures 失效
    包括鳍结构的非易失性存储单元

    公开(公告)号：US07737485B2

    公开(公告)日：2010-06-15

    申请号：US12193200

    申请日：2008-08-18

    申请人： Eun-Suk Cho ,  Choong-Ho Lee ,  Tae-Yong Kim

    发明人： Eun-Suk Cho ,  Choong-Ho Lee ,  Tae-Yong Kim

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42316 ,  H01L29/42324 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/792

    摘要： A method of forming a non-volatile memory device may include forming a fin protruding from a substrate, forming a tunnel insulating layer on portions of the fin, and forming a floating gate on the tunnel insulting layer so that the tunnel insulating layer is between the floating gate and the fin. A dielectric layer may be formed on the floating gate so that the floating gate is between the dielectric layer and the fin, and a control gate electrode may be formed on the dielectric layer so that the dielectric layer is between the control gate and the fin. Related devices are also discussed.

    摘要翻译： 形成非易失性存储器件的方法可以包括形成从衬底突出的翅片，在鳍的部分上形成隧道绝缘层，并且在隧道绝缘层上形成浮栅，使得隧道绝缘层在 浮动门和鳍。 可以在浮置栅极上形成电介质层，使得浮置栅极位于电介质层和鳍之间，并且可以在电介质层上形成控制栅电极，使得电介质层位于控制栅和鳍之间。 还讨论了相关设备。

    Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions
    9.
    发明申请
    Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
    制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法

    公开(公告)号：US20070048934A1

    公开(公告)日：2007-03-01

    申请号：US11505335

    申请日：2006-08-17

    申请人： Suk-Pil Kim ,  Yoon-Dong Park ,  Won-Joo Kim ,  Dong-Gun Park ,  Eun-Suk Cho ,  Suk-Kang Sung ,  Byung-Yong Choi ,  Tae-Yong Kim ,  Choong-Ho Lee

    发明人： Suk-Pil Kim ,  Yoon-Dong Park ,  Won-Joo Kim ,  Dong-Gun Park ,  Eun-Suk Cho ,  Suk-Kang Sung ,  Byung-Yong Choi ,  Tae-Yong Kim ,  Choong-Ho Lee

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/785 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/1159 ,  H01L27/2436 ,  H01L29/66795

    摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.

    摘要翻译： 提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法，显示出与SOI结构相关的一些特征优点，提供增加的工作电流和/或降低的接触电阻。 制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域，从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。 在形成翅片之后，形成第三绝缘膜以填充第二沟槽并支撑翅片。 然后去除第一绝缘膜的一部分以打开翅片之间的空间，其中可以形成包括栅极电介质，栅电极和附加接触，绝缘和存储节点结构的附加结构。