摘要:
A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.
摘要:
A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.
摘要:
A method of operating a cross-point memory device, having an array of multilevel cells, includes performing a first reading operation with respect to the multilevel cells through a plurality of sensing operations to determine a first state and performing a second reading operation with respect to the multilevel cells through a plurality of sensing operations to determine a second state. A difference between a level of a first voltage used in a first sensing operation and a level of a second voltage used in a second sensing operation in the first reading operation is different from a difference between a level of a third voltage used in a first sensing operation and a level of a fourth voltage used in a second sensing operation in the second reading operation.
摘要:
A method of operating a memory system including memory cells commonly connected to a first signal line in a memory cell array includes; dividing the memory cells according to cell regions, and independently performing read operations on memory cells disposed in each cell region using a read reference selected from a plurality of read references and respectively corresponding to each cell region.
摘要:
A resistive memory device includes a column decoder having a first switch unit, including at least one pair of switches arranged in correspondence to each of a plurality of signal lines, and a second switch unit including a pair of switches arranged in correspondence to the at least one pair of switches of the first switch unit. A first pair of switches of the first switch unit includes a first switch and a second switch that are of the same type, and a second pair of switches of the second switch unit includes a third switch and a fourth switch that are connected to the first pair of switches. A selection voltage is provided to the first signal line by passing through the first switch, and an inhibit voltage is provided to the first signal line by selectively passing through the first switch or the second switch.
摘要:
A memory device includes a memory cell array having multiple memory cells arranged respectively in regions where first signal lines cross second signal lines. The memory device further includes a decoder having multiple line selection switch units connected respectively to the of first signal lines. Each of the multiple line selection switch units applies a bias voltage to a first signal line corresponding to each of the multiple line selection switch units in response selectively to a first switching signal and a second switching signal, voltage levels of which are different from each other in activated states.
摘要:
A three-dimensional (3D) semiconductor memory device comprises memory cell strings each comprising at least one selection transistor and at least one memory cell, a first pass transistor group sharing a first well region and comprising a first selection line pass transistor connected to the selection transistor and a first world line pass transistor connected to the memory cell, a second pass transistor group sharing a second well region and comprising a second selection line pass transistor connected to the selection transistor, and a controller that controls the first pass transistor group and the second pass transistor group. The controller applies selected voltages to the first and second well regions during read operation.