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    System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device
    1.
    发明授权
    System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device 有权
    用于提供聚盖和无场氧化物区域以防止在半导体器件的制造中形成垂直鸟嘴结构的系统和方法

    公开(公告)号：US07488647B1

    公开(公告)日：2009-02-10

    申请号：US11201761

    申请日：2005-08-11

    Applicant: Charles A. Dark ,  Andy Strachan

    Inventor： Charles A. Dark ,  Andy Strachan

    IPC: H01L21/336 ,  H01L21/76 ,  H01L21/4763

    CPC classification number: H01L21/763 ,  H01L21/76202

    Abstract: A system and method is disclosed that prevents the formation of a vertical bird's beak structure in the manufacture of a semiconductor device. A polysilicon filled trench is formed in a substrate of the semiconductor device. One or more composite layers are then applied over the trench and the substrate. A mask and etch process is then applied to etch the composite layers adjacent to the polysilicon filled trench. A field oxide process is applied to form field oxide portions in the substrate adjacent to the trench. Because no field oxide is placed over the trench there is no formation of a vertical bird's beak structure. A gate oxide layer is applied and a protection cap is formed over the polysilicon filled trench to protect the trench from unwanted effects of subsequent processing steps.

    Abstract translation: 公开了一种系统和方法，其防止在制造半导体器件时形成垂直鸟喙结构。 在半导体器件的衬底中形成多晶硅填充沟槽。 然后将一个或多个复合层施加在沟槽和衬底上。 然后施加掩模和蚀刻工艺以蚀刻与多晶硅填充沟槽相邻的复合层。 施加场氧化物工艺以在与沟槽相邻的衬底中形成场氧化物部分。 由于没有将场氧化物放置在沟槽上，所以没有形成垂直鸟的喙结构。 施加栅极氧化物层，并且在多晶硅填充的沟槽上形成保护帽，以保护沟槽免受后续处理步骤的不期望的影响。

    System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device
    4.
    发明授权
    System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device 有权
    用于提供聚盖和无场氧化物区域以防止在半导体器件的制造中形成垂直鸟嘴结构的系统和方法

    公开(公告)号：US07989883B1

    公开(公告)日：2011-08-02

    申请号：US12321205

    申请日：2009-01-16

    Applicant: Charles A. Dark ,  Andy Strachan

    Inventor： Charles A. Dark ,  Andy Strachan

    IPC: H01L29/66

    CPC classification number: H01L21/763 ,  H01L21/76202

    Abstract: A system and method is disclosed that prevents the formation of a vertical bird's beak structure in the manufacture of a semiconductor device. A polysilicon filled trench is formed in a substrate of the semiconductor device. One or more composite layers are then applied over the trench and the substrate. A mask and etch process is then applied to etch the composite layers adjacent to the polysilicon filled trench. A field oxide process is applied to form field oxide portions in the substrate adjacent to the trench. Because no field oxide is placed over the trench there is no formation of a vertical bird's beak structure. A gate oxide layer is applied and a protection cap is formed over the polysilicon filled trench to protect the trench from unwanted effects of subsequent processing steps.

    Abstract translation: 公开了一种系统和方法，其防止在制造半导体器件时形成垂直鸟喙结构。 在半导体器件的衬底中形成多晶硅填充沟槽。 然后将一个或多个复合层施加在沟槽和衬底上。 然后施加掩模和蚀刻工艺以蚀刻与多晶硅填充沟槽相邻的复合层。 施加场氧化物工艺以在与沟槽相邻的衬底中形成场氧化物部分。 由于没有将场氧化物放置在沟槽上，所以没有形成垂直鸟的喙结构。 施加栅极氧化物层，并且在多晶硅填充的沟槽上形成保护帽，以保护沟槽免受后续处理步骤的不期望的影响。

    Electrical test structure and method for characterization of deep trench sidewall reliability
    5.
    发明授权
    Electrical test structure and method for characterization of deep trench sidewall reliability 有权
    用于表征深沟侧壁可靠性的电气测试结构和方法

    公开(公告)号：US07960998B2

    公开(公告)日：2011-06-14

    申请号：US12212289

    申请日：2008-09-17

    Applicant: Lisa V. Rozario ,  Andy Strachan ,  Richard Orr

    Inventor： Lisa V. Rozario ,  Andy Strachan ,  Richard Orr

    IPC: G01R31/02

    CPC classification number: G01R31/2623 ,  G01R31/2639 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A test structure and testing method are provided for characterizing the time-dependent drift in the parasitic PFET leakage current that flows along the sidewall of a deep trench isolation structure from the P-type active area to the P-type substrate in a semiconductor integrated circuit structure. The capacitive coupling characteristics of the deep trench isolation structure are used to control the electrical “bias” of the deep trench structure through the use of a large auxiliary trench mesh network that is formed as part of the deep trench structure. The trench mesh network can be placed adjacent to a Vdd ring or a ground ring and then, by using a ratioed capacitive voltage dividing network, the electrical potential at the trench can be controlled.

    Abstract translation: 提供了一种测试结构和测试方法，用于表征在半导体集成电路中沿着深沟槽隔离结构的侧壁从P型有源区流向P型衬底的寄生PFET漏电流中的时间依赖性漂移 结构体。 深沟槽隔离结构的电容耦合特性用于通过使用形成为深沟槽结构的一部分的大的辅助沟槽网状网来控制深沟槽结构的电“偏置”。 沟槽网状网络可以靠近Vdd环或接地环放置，然后通过使用比例的电容分压网络，可以控制沟槽处的电位。

    LDMOS transistor structure for improving hot carrier reliability
    7.
    发明授权
    LDMOS transistor structure for improving hot carrier reliability 有权
    LDMOS晶体管结构，用于提高热载流子的可靠性

    公开(公告)号：US06946706B1

    公开(公告)日：2005-09-20

    申请号：US10616381

    申请日：2003-07-09

    Applicant: Douglas Brisbin ,  David Tsuei ,  Alexander H. Owens ,  Andy Strachan

    Inventor： Douglas Brisbin ,  David Tsuei ,  Alexander H. Owens ,  Andy Strachan

    IPC: H01L29/06 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

    CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/4238

    Abstract: An LDMOS structure which provides for reduced hot carrier effects. The reduction in hot carrier effects is achieved by increasing the size of the drain region of the LDMOS relative to the size of the source region. The larger size of the drain region reduces the concentration of electrons entering the drain region. This reduction in the concentration of electrons reduces the number of impact ionizations, which in turn reduces the hot carrier effects. The overall performance of the LDMOS is improved by reducing the hot carrier effects.

    Abstract translation: 提供减少热载体效应的LDMOS结构。 通过增加LDMOS的漏极区域相对于源极区域的尺寸来实现热载流子效应的降低。 漏极区域的较大尺寸减小了进入漏极区域的电子的浓度。 电子浓度的这种降低减少了冲击电离的数量，这又降低了热载流子的影响。 通过减少热载体效应，提高了LDMOS的整体性能。

    ELECTRICAL TEST STRUCTURE AND METHOD FOR CHARACTERIZATION OF DEEP TRENCH SIDEWALL RELIABILITY
    9.
    发明申请
    ELECTRICAL TEST STRUCTURE AND METHOD FOR CHARACTERIZATION OF DEEP TRENCH SIDEWALL RELIABILITY 有权
    电气测试结构及其深度稳定性可靠性特征的方法

    公开(公告)号：US20090206865A1

    公开(公告)日：2009-08-20

    申请号：US12212289

    申请日：2008-09-17

    Applicant: Lisa V. Rozario ,  Andy Strachan ,  Richard Orr

    Inventor： Lisa V. Rozario ,  Andy Strachan ,  Richard Orr

    IPC: G01R31/26 ,  H01L23/58

    CPC classification number: G01R31/2623 ,  G01R31/2639 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A test structure and testing method are provided for characterizing the time-dependent drift in the parasitic PFET leakage current that flows along the sidewall of a deep trench isolation structure from the P-type active area to the P-type substrate in a semiconductor integrated circuit structure. The capacitive coupling characteristics of the deep trench isolation structure are used to control the electrical “bias” of the deep trench structure through the use of a large auxiliary trench mesh network that is formed as part of the deep trench structure. The trench mesh network can be placed adjacent to a Vdd ring or a ground ring and then, by using a ratioed capacitive voltage dividing network, the electrical potential at the trench can be controlled.

    Abstract translation: 提供了一种测试结构和测试方法，用于表征在半导体集成电路中沿着深沟槽隔离结构的侧壁从P型有源区流向P型衬底的寄生PFET漏电流中的时间依赖性漂移 结构体。 深沟槽隔离结构的电容耦合特性用于通过使用形成为深沟槽结构的一部分的大的辅助沟槽网状网来控制深沟槽结构的电“偏置”。 沟槽网状网络可以靠近Vdd环或接地环放置，然后通过使用比例的电容分压网络，可以控制沟槽处的电位。

    Method of measuring the leakage current of a deep trench isolation structure
    10.
    发明授权
    Method of measuring the leakage current of a deep trench isolation structure 有权
    测量深沟槽隔离结构的漏电流的方法

    公开(公告)号：US07298159B1

    公开(公告)日：2007-11-20

    申请号：US11176994

    申请日：2005-07-07

    Applicant: Lisa V. Rozario ,  Andy Strachan

    Inventor： Lisa V. Rozario ,  Andy Strachan

    IPC: G01R31/26 ,  G01R31/00

    CPC classification number: G01R31/2623

    Abstract: The trench leakage current of a deep trench isolation structure is measured. The deep trench isolation structure, which is filled with polysilicon, contacts both a first region of a first conductivity type and a second region of a second conductivity type, and is proximate to a third region of the first conductivity type formed in the second region. Test voltages are applied to the structures and the leakage current is measured.

    Abstract translation: 测量深沟槽隔离结构的沟槽漏电流。 填充有多晶硅的深沟槽隔离结构与第一导电类型的第一区域和第二导电类型的第二区域接触，并且接近形成在第二区域中的第一导电类型的第三区域。 对结构施加测试电压，并测量泄漏电流。

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