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公开(公告)号：US4999815A
公开(公告)日：1991-03-12
申请号：US479137
申请日：1990-02-13
申请人： John E. Barth, Jr. , Charles E. Drake , William P. Hovis , Howard L. Kalter , Gordon A. Kelley, Jr. , Scott C. Lewis , Daniel J. Nickel , James A. Yankosky
发明人： John E. Barth, Jr. , Charles E. Drake , William P. Hovis , Howard L. Kalter , Gordon A. Kelley, Jr. , Scott C. Lewis , Daniel J. Nickel , James A. Yankosky
IPC分类号： G11C11/41 , G11C8/10 , G11C8/12 , G11C8/18 , G11C11/401 , G11C11/406
摘要： Low power addressing systems are provided which include a given number of memory segments, each having word and bit/sense lines, a given number of decoders coupled to the given number of memory segments for selecting one word line in each of the memory segments, a first plurality of transmission gate systems, each having first and second transmission gates, with each of the gates being coupled to a different one of the decoders, a second decoder having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems, first control circuits for selectively activating the first and second gates in each of the first plurality of transmission gate systems, a second given number of decoders coupled to the given number of memory segments for selecting one bit/sense line in each of the memory segments, a second plurality of transmission gate systems, each having first and second transmission gates, with each of the gates of the second plurality of transmission gate systems being coupled to a different one of the second given number of decoders, and second control circuits for selectively activating the first and second gates of each of the second plurality of transmission gate systems.
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2.发明授权
公开(公告)号：US5134616A
公开(公告)日：1992-07-28
申请号：US479145
申请日：1990-02-13
申请人： John E. Barth, Jr. , Charles E. Drake , John A. Fifield , William P. Hovis , Howard L. Kalter , Scott C. Lewis , Daniel J. Nickel , Charles H. Stapper , James A. Yankosky
发明人： John E. Barth, Jr. , Charles E. Drake , John A. Fifield , William P. Hovis , Howard L. Kalter , Scott C. Lewis , Daniel J. Nickel , Charles H. Stapper , James A. Yankosky
IPC分类号： G11C11/401 , G06F11/10 , G11C29/00 , G11C29/42
CPC分类号： G11C29/84 , G06F11/1008
摘要： A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block provides both the corrected data bits and the check bits to an SRAM. Thus, the check bits can be externally accessed. At the same time, having a set of interrelated bits in the SRAM compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.
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公开(公告)号：US5015880A
公开(公告)日：1991-05-14
申请号：US419341
申请日：1989-10-10
IPC分类号： H03K17/687 , H03K17/04 , H03K19/003 , H03K19/017 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/00361 , H03K19/01721
摘要： A CMOS integrated circuit for driving capacitance devices is provided. The circuit has an input node and an output node and includes a first transistor operatively connected to the input node which is turned "on" and "off" by the input node to supply an output signal to the output node when turned "on". A second transistor is provided, the output of which is connected to the output node when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor prior to the second transistor, and to turn on the second transistor if and only if the slew rate of the output signal of the first transistor is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor; however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor will cause the second transistor to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.
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公开(公告)号：US5604755A
公开(公告)日：1997-02-18
申请号：US565627
申请日：1995-11-20
CPC分类号： G06F11/1024 , G06F11/073 , G06F11/0793 , G11C5/005 , G06F11/0796
摘要： A reset circuit for resetting a memory system following a radiation event includes an error detect circuit for producing an error signal in response to detection of an uncorrectable error in the systems memory arrays, and includes a control circuit for selectively resetting at least select portions of the memory system in response to the error detect signal. All or portions of the memory arrays can be reset by the control circuit, and complete or selective latch reset, or selective power recycling are provided. In one embodiment, the control circuit provides latch reset in response to the error detect signal so as to reset the memory latches without recycling power, and in another embodiment, the control circuit selectively cycles power to independent memory zones of the system to reset only those zones whose memory array is identified as having an uncorrectable error. Preferably, the control circuit, and perhaps the detect circuit, are radiation hardened to further ensure dependable operation of the reset circuit following a radiation event.
摘要翻译： 用于在辐射事件之后复位存储器系统的复位电路包括：误差检测电路，用于响应于系统存储器阵列中的不可校正误差的检测而产生误差信号，并且包括控制电路，用于至少选择性地复位 存储器系统响应于错误检测信号。 存储器阵列的全部或部分可由控制电路复位，并提供完整的或选择性的锁存复位或选择性的电力回收。 在一个实施例中，控制电路响应于错误检测信号提供锁存器复位，以便在不再循环功率的情况下复位存储器锁存器，并且在另一实施例中，控制电路选择性地将电力循环到系统的独立存储器区域，以仅复位那些 存储器阵列被识别为具有不可校正错误的区域。 优选地，控制电路以及可能的检测电路被辐射硬化，以进一步确保在辐射事件之后复位电路的可靠操作。
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公开(公告)号：US5535226A
公开(公告)日：1996-07-09
申请号：US251056
申请日：1994-05-31
CPC分类号： G06F11/1008 , G06F11/1024
摘要： In one aspect, a memory device employing device-level error correction tracks the status of the error correction in terms of whether error correction is active or inactive, whether an uncorrectable error beyond the capability of the device-level correction is detected, whether a recovery option from an uncorrectable error is active and whether the recovery option has been reset. In another aspect, a diagnostic method for determining a status for one or more aspects of device-level error correction employed by a memory device is provided. In the diagnostic method, the status is determined for the one or more aspects, a flag is set based on the status, the flag is latched, a diagnostic code is input into the memory device and the latched flag is read.
摘要翻译： 在一个方面，采用设备级错误校正的存储器件根据纠错是有效还是无效来跟踪纠错的状态，是否检测到超出设备级校正能力的不可校正错误，是否恢复 来自不可校正错误的选项处于活动状态，以及恢复选项是否已重置。 另一方面，提供了一种用于确定存储器件所采用的器件级错误校正的一个或多个方面的状态的诊断方法。 在诊断方法中，针对一个或多个方面确定状态，基于状态设置标志，锁存标志，将诊断代码输入到存储器件中，并且读取锁存标志。
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