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    Semiconductor arrangement preventing damage during contact processing
    6.
    发明授权
    Semiconductor arrangement preventing damage during contact processing 失效
    半导体布置防止接触处理过程中的损坏

    公开(公告)号：US06188124B1

    公开(公告)日：2001-02-13

    申请号：US09354374

    申请日：1999-07-14

    申请人： Gregory S. Boettcher ,  Robert P. Katz ,  Ashwani K. Malhotra ,  James Wood

    发明人： Gregory S. Boettcher ,  Robert P. Katz ,  Ashwani K. Malhotra ,  James Wood

    IPC分类号： H01L23544

    CPC分类号： H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor arrangement having a first active region and a dummy region on a surface of a substrate. The first active region and the dummy region are spaced from one another without any contact, and the dummy region is closer to an edge of the surface of the substrate in comparison to the first active region. Formed on the dummy region, first active region, and a portion of the substrate surface is a dielectric layer. The surface of the dielectric layer has an inactive portion and an active portion. A mask is disposed on the dielectric layer such that the mask contacts the inactive portion and does not contact the active portion.

    摘要翻译： 一种在衬底表面上具有第一有源区和虚拟区的半导体装置。 与第一有源区域相比，第一有源区域和虚设区域彼此间隔开而没有任何接触，并且虚设区域更靠近衬底的表面的边缘。 在虚拟区域上形成第一有源区，并且衬底表面的一部分是电介质层。 电介质层的表面具有非活性部分和活性部分。 掩模设置在电介质层上，使得掩模接触非活性部分并且不接触有源部分。

    Process for transferring a thin-film structure to a substrate
    7.
    发明授权
    Process for transferring a thin-film structure to a substrate 失效
    将薄膜结构转印到基板的方法

    公开(公告)号：US06183588B2

    公开(公告)日：2001-02-06

    申请号：US09460488

    申请日：1999-12-14

    申请人： Kimberley A. Kelly ,  Ashwani K. Malhotra ,  Eric D. Perfecto ,  Roy Yu

    发明人： Kimberley A. Kelly ,  Ashwani K. Malhotra ,  Eric D. Perfecto ,  Roy Yu

    IPC分类号： B32B3100

    CPC分类号： B32B43/00 ,  B32B2310/0843 ,  B32B2311/00 ,  H01L21/6835 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2924/3025 ,  H05K3/007 ,  H05K3/025 ,  H05K3/28 ,  H05K3/4614 ,  H05K3/4623 ,  H05K3/467 ,  H05K2201/09527 ,  H05K2201/10666 ,  H05K2203/016 ,  H05K2203/107 ,  Y10S156/922 ,  Y10S438/94 ,  Y10S438/974 ,  Y10S438/977 ,  Y10T156/11 ,  Y10T156/1158 ,  Y10T428/12528 ,  Y10T428/12583

    摘要： A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing. The process of the present invention has at least three, specific applications: (1) the thin-film structure and metal interconnect can be released to yield a free-standing film; (2) the thin-film structure and metal interconnect can be laminated onto a permanent substrate (when building top-side down structures) and then released; and (3) the thin-film structure can be transferred to a secondary temporary carrier (when building top-side up structures) for further processing and testing, then transferred to a permanent substrate before releasing the thin-film structure and metal interconnect.

    摘要翻译： 用于从主载体制造和释放薄膜结构以进一步处理的工艺。 薄膜结构建立在设置在电介质层上的金属互连上，其又沉积在主载体上。 薄膜结构和金属互连通过限定在金属互连和电介质膜之间的释放界面从电介质层和初级载体释放。 通过激光烧蚀或切割来干扰界面来实现释放。 本发明的方法具有至少三个具体应用：（1）可以释放薄膜结构和金属互连以产生独立的膜; （2）薄膜结构和金属互连可以层压在永久性基板上（当构建顶部向下结构时）然后释放; （3）可以将薄膜结构转移到二次临时载体（当构建顶侧上部结构）进行进一步的加工和测试时，在释放薄膜结构和金属互连之前转移到永久基板。

    In-line voltage plane tests for multi-chip modules
    9.
    发明授权
    In-line voltage plane tests for multi-chip modules 失效
    多芯片模块的在线电压平面测试

    公开(公告)号：US6002267A

    公开(公告)日：1999-12-14

    申请号：US898757

    申请日：1997-07-23

    申请人： Ashwani K. Malhotra ,  John R. Pennacchia ,  Ronald R. Shields ,  Thomas A. Wassick

    发明人： Ashwani K. Malhotra ,  John R. Pennacchia ,  Ronald R. Shields ,  Thomas A. Wassick

    IPC分类号： G01R1/073 ,  G01R31/02

    CPC分类号： G01R1/07378

    摘要： A test pad is formed outside an array of pads included in connection structures such as pin mounting pads to which connection pins may be brazed in, for example, bottom side metallurgy of a multi-layer modular electronic package. In-line voltage plane testing may then be accomplished through temporary connections to the test pads for any desired layer, such as top side metallurgy distribution layers, while protecting the pin-mounting pads from physical and/or chemical damage or contamination during manufacturing processes for addition of layers to the electrical interconnection structure of the multi-layer module.

    摘要翻译： 在诸如销安装焊盘的连接结构中包括的焊盘阵列外部形成测试焊盘，连接引脚可以钎焊到例如多层模块化电子封装的底侧冶金中。 然后可以通过临时连接到用于任何所需层（例如顶侧冶金分布层）的测试焊盘来实现在线电压平面测试，同时在制造过程中保护销安装垫免受物理和/或化学损坏或污染 向多层模块的电互连结构添加层。