公开(公告)号：US07851911B2

公开(公告)日：2010-12-14

申请号：US12715523

申请日：2010-03-02

申请人： Charles F. Carey ,  Bernt Julius Hansen ,  Ashwani K. Malhotra ,  David L. Questad ,  Wolfgang Sauter

发明人： Charles F. Carey ,  Bernt Julius Hansen ,  Ashwani K. Malhotra ,  David L. Questad ,  Wolfgang Sauter

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L22/34 ,  H01L22/14 ,  H01L22/32 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2924/014 ,  H05K1/0268 ,  H05K3/3436 ,  H05K2203/163 ,  Y02P70/613 ,  H01L2924/00014

摘要： A semiconductor chip for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.

摘要翻译： 用于形成该半导体芯片的半导体芯片。 半导体芯片包括M个常规焊料凸块结构和N个监测焊料凸块结构，M和N是正整数。 如果对半导体芯片执行倒装芯片处理，则N监视器焊料凸块结构对于冷却压力比对M规则焊料凸块结构更敏感。 冷却应力来自倒装芯片工艺的冷却步骤。 每个M规则焊料凸块结构电连接到电源或半导体芯片的器件。 N个监视器焊料凸块结构中的每一个都不电连接到电源或半导体芯片的器件。

公开(公告)号：US07674637B2

公开(公告)日：2010-03-09

申请号：US11749885

申请日：2007-05-17

申请人： Charles F. Carey ,  Bernt Julius Hansen ,  Ashwani K. Malhotra ,  David L. Questad ,  Wolfgang Sauter

发明人： Charles F. Carey ,  Bernt Julius Hansen ,  Ashwani K. Malhotra ,  David L. Questad ,  Wolfgang Sauter

IPC分类号： G01L31/26 ,  H01L21/66

CPC分类号： H01L22/34 ,  H01L22/14 ,  H01L22/32 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2924/014 ,  H05K1/0268 ,  H05K3/3436 ,  H05K2203/163 ,  Y02P70/613 ,  H01L2924/00014

摘要： A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.

摘要翻译： 半导体芯片及其形成方法。 半导体芯片包括M个常规焊料凸块结构和N个监测焊料凸块结构，M和N是正整数。 如果对半导体芯片执行倒装芯片处理，则N监视器焊料凸块结构对于冷却压力比对M规则焊料凸块结构更敏感。 冷却应力来自倒装芯片工艺的冷却步骤。 每个M规则焊料凸块结构电连接到电源或半导体芯片的器件。 N个监视器焊料凸块结构中的每一个都不电连接到电源或半导体芯片的器件。

公开(公告)号：US20080286886A1

公开(公告)日：2008-11-20

申请号：US11749885

申请日：2007-05-17

申请人： Charles F. Carey ,  Bernt Julius Hansen ,  Ashwani K. Malhotra ,  David L. Questad ,  Wolfgang Sauter

发明人： Charles F. Carey ,  Bernt Julius Hansen ,  Ashwani K. Malhotra ,  David L. Questad ,  Wolfgang Sauter

IPC分类号： H01L21/66 ,  H01L23/58

CPC分类号： H01L22/34 ,  H01L22/14 ,  H01L22/32 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2924/014 ,  H05K1/0268 ,  H05K3/3436 ,  H05K2203/163 ,  Y02P70/613 ,  H01L2924/00014

摘要： A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.

摘要翻译： 半导体芯片及其形成方法。 半导体芯片包括M个常规焊料凸块结构和N个监测焊料凸块结构，M和N是正整数。 如果对半导体芯片执行倒装芯片处理，则N监视器焊料凸块结构对于冷却压力比对M规则焊料凸块结构更敏感。 冷却应力来自倒装芯片工艺的冷却步骤。 每个M规则焊料凸块结构电连接到电源或半导体芯片的器件。 N个监视器焊料凸块结构中的每一个都不电连接到电源或半导体芯片的器件。

公开(公告)号：US20100155943A1

公开(公告)日：2010-06-24

申请号：US12715523

申请日：2010-03-02

申请人： Charles F. Carey ,  Bernt Julius Hansen ,  Ashwani K. Malhotra ,  David L. Questad ,  Wolfgang Sauter

发明人： Charles F. Carey ,  Bernt Julius Hansen ,  Ashwani K. Malhotra ,  David L. Questad ,  Wolfgang Sauter

IPC分类号： H01L23/498

CPC分类号： H01L22/34 ,  H01L22/14 ,  H01L22/32 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2924/014 ,  H05K1/0268 ,  H05K3/3436 ,  H05K2203/163 ,  Y02P70/613 ,  H01L2924/00014

摘要： A semiconductor chip for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.

摘要翻译： 用于形成该半导体芯片的半导体芯片。 半导体芯片包括M个常规焊料凸块结构和N个监测焊料凸块结构，M和N是正整数。 如果对半导体芯片执行倒装芯片处理，则N监视器焊料凸块结构对于冷却压力比对M规则焊料凸块结构更敏感。 冷却应力来自倒装芯片工艺的冷却步骤。 每个M规则焊料凸块结构电连接到电源或半导体芯片的器件。 N个监视器焊料凸块结构中的每一个都不电连接到电源或半导体芯片的器件。

公开(公告)号：US5597469A

公开(公告)日：1997-01-28

申请号：US387686

申请日：1995-02-13

申请人： Charles F. Carey ,  Kenneth M. Fallon ,  Voya R. Markovich ,  Douglas O. Powell ,  Gary P. Vlasak ,  Richard S. Zarr

发明人： Charles F. Carey ,  Kenneth M. Fallon ,  Voya R. Markovich ,  Douglas O. Powell ,  Gary P. Vlasak ,  Richard S. Zarr

IPC分类号： C25D5/02 ,  C25D5/08 ,  H01L21/48 ,  H01L21/60 ,  H05K3/24 ,  H05K3/34

CPC分类号： H01L24/81 ,  C25D5/022 ,  C25D5/08 ,  H01L21/4825 ,  H01L21/4853 ,  H05K3/241 ,  H05K3/3473 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H05K2203/043 ,  H05K2203/054

摘要： Small, closely spaced deposits of solder materials may be formed with high volumetric accuracy and uniformity of shape by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching and reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Uniformity of electroplating within blind apertures is enhanced by a combination of fluid jet sparging and cathode agitation. Excess conductor material in the resulting solder deposit can be avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to electroplating.

摘要翻译： 可以通过在具有孔或凹槽（例如盲孔）的电介质层的表面上沉积导电材料层并且暴露于其中的导体和/或焊盘而形成具有高体积精度和形状均匀性的小的，紧密间隔的焊料材料沉积物 孔或凹槽，导电材料的掩模区域和另外的图案化介电层，将电镀焊料材料电镀到由掩模曝光的导电材料的区域上，通过选择性蚀刻和至少从至少 有孔电介质层的一部分表面。 盲孔内电镀的均匀性通过流体喷射和阴极搅拌的组合增强。 在电镀之前，可以通过在浸没池中用焊料材料的构成成分代替导体材料来避免所得到的焊料沉积物中的过多的导体材料。

公开(公告)号：US07119003B2

公开(公告)日：2006-10-10

申请号：US11148923

申请日：2005-06-08

申请人： William E. Bernier ,  Charles F. Carey ,  Eberhard B. Gramatzki ,  Thomas R. Homa ,  Eric A. Johnson ,  Pierre Langevin ,  Irving Memis ,  Son K. Tran ,  Robert F. White

发明人： William E. Bernier ,  Charles F. Carey ,  Eberhard B. Gramatzki ,  Thomas R. Homa ,  Eric A. Johnson ,  Pierre Langevin ,  Irving Memis ,  Son K. Tran ,  Robert F. White

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/351 ,  H05K3/3436 ,  H01L2924/00

摘要： A method and structure for coupling a semiconductor substrate (e.g., a semiconductor chip) to an organic substrate (e.g., a chip carrier). The coupling interfaces a solder member (e.g., a solder ball) to both a conductive pad on the semiconductor substrate and a conductive pad on the organic substrate. Thermal strains on the solder member during thermal cycling may be reduced by having a surface area of the pad on the semiconductor substrate exceed a surface area of the pad on the organic substrate. Thermal strains on the solder member during thermal cycling may also be reduced by having a distance from a centerline of the solder member to a closest lateral edge of the semiconductor substrate exceed about 0.25 mm.

公开(公告)号：US5075965A

公开(公告)日：1991-12-31

申请号：US608766

申请日：1990-11-05

申请人： Charles F. Carey ,  Kenneth M. Fallon ,  Rochelle Ginsburg ,  Charles G. Woychik

发明人： Charles F. Carey ,  Kenneth M. Fallon ,  Rochelle Ginsburg ,  Charles G. Woychik

IPC分类号： B23K1/00 ,  H01L21/60 ,  H05K3/34

CPC分类号： H01L24/81 ,  B23K1/0016 ,  H05K3/3436 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K2201/10992 ,  H05K2203/0415 ,  H05K3/3431 ,  H05K3/3457 ,  Y02P70/613 ,  Y10T29/49144

摘要： A controlled collapse chip connect method of joining an IC chip to a microelectronic circuit card. According to the method an inhomogeneous, anisotropic column of solder is deposited from a Pb/Sn alloy onto solder wettable I/O terminals of the I/C chip, without subsequent homogenizing reflow. The solder core has a Pb rich core and an Sn rich cap. The matching footprint of the solder wettable I/O terminals on the microelectronic circuit card is substantially free of deposited solder and presents a protected Cu surface to the solder columns, or, at most a surface of Cu and anti-oxidant. The chip is aligned with the corresponding footprints on the microelectronic circuit card, and the solder is reflowed to bond the chip to the microelectronic circuit card.

公开(公告)号：US07067916B2

公开(公告)日：2006-06-27

申请号：US09885853

申请日：2001-06-20

申请人： William E. Bernier ,  Charles F. Carey ,  Eberhard B. Gramatzki ,  Thomas R. Homa ,  Eric A. Johnson ,  Pierre Langevin ,  Irving Memis ,  Son K. Tran ,  Robert F. White

发明人： William E. Bernier ,  Charles F. Carey ,  Eberhard B. Gramatzki ,  Thomas R. Homa ,  Eric A. Johnson ,  Pierre Langevin ,  Irving Memis ,  Son K. Tran ,  Robert F. White

IPC分类号： H01L23/48

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/351 ,  H05K3/3436 ,  H01L2924/00

摘要： A method and structure for coupling a semiconductor substrate (e.g., a semiconductor chip) to an organic substrate (e.g., a chip carrier). The coupling interfaces a solder member (e.g., a solder ball) to both a conductive pad on the semiconductor substrate and a conductive pad on the organic substrate. Thermal strains on the solder member during thermal cycling may be reduced by having a surface area of the pad on the semiconductor substrate exceed a surface area of the pad on the organic substrate. Thermal strains on the solder member during thermal cycling may also be reduced by having a distance from a centerline of the solder member to a closest lateral edge of the semiconductor substrate exceed about 0.25 mm.

公开(公告)号：US06677522B1

公开(公告)日：2004-01-13

申请号：US10255457

申请日：2002-09-26

申请人： Charles F. Carey ,  Eric A. Johnson ,  Alfredo Migliore

发明人： Charles F. Carey ,  Eric A. Johnson ,  Alfredo Migliore

IPC分类号： H01L2328

CPC分类号： H01L23/562 ,  H01L23/3121 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： An electronic component such as a ceramic capacitor is coupled to a dielectric substrate package. Encapsulant material substantially surrounding the sides of the component, develops cracks therein, particularly near the corners of the component where CTE stresses are greatest. The cracks propagate downward into the dielectric substrate material and sever circuit lines in the substrate causing failure. A mounting pad for the component is extended from beneath the component to substantially beyond the outer periphery of the encapsulant material to prevent cracks from propagating into the dielectric material.

摘要翻译： 诸如陶瓷电容器的电子部件耦合到电介质基板封装。 基本上围绕部件侧面的封装材料在其中产生裂纹，特别是在CTE应力最大的部件的拐角附近。 裂纹向下传播到电介质基片材料中，并使基片中的电路线导致故障。 用于部件的安装垫从部件下方延伸到基本上超过密封剂材料的外周边，以防止裂纹传播到电介质材料中。