公开(公告)号：US06617242B1

公开(公告)日：2003-09-09

申请号：US08480543

申请日：1995-06-07

申请人： Fusen E. Chen ,  Fu-Tai Liou ,  Timothy E. Turner ,  Che-Chia Wei ,  Yih-Shung Lin ,  Girish Anant Dixit

发明人： Fusen E. Chen ,  Fu-Tai Liou ,  Timothy E. Turner ,  Che-Chia Wei ,  Yih-Shung Lin ,  Girish Anant Dixit

IPC分类号： H01L2144

CPC分类号： H01L21/76858 ,  H01L21/28512 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating interlevel contacts in semiconductor integrated circuits provides for formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

摘要翻译： 在半导体集成电路中制造层间接触的方法提供通过绝缘层形成接触开口。 一层难熔金属或难熔金属合金沉积在集成电路芯片的表面上。 然后在显着提高的温度下沉积铝层，使得在铝层和难熔金属层之间的界面处形成铝/难熔金属合金。 这种合金的形成导致接触开口内的金属膨胀，从而填充接触开口并为沉积的铝层提供光滑的上部轮廓。

公开(公告)号：US06242811B1

公开(公告)日：2001-06-05

申请号：US09080066

申请日：1998-05-15

申请人： Fusen E. Chen ,  Fu-Tai Liou ,  Timothy E. Turner ,  Che-Chia Wei ,  Yih-Shung Lin ,  Girish Anant Dixit

发明人： Fusen E. Chen ,  Fu-Tai Liou ,  Timothy E. Turner ,  Che-Chia Wei ,  Yih-Shung Lin ,  Girish Anant Dixit

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/28512 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interlevel contacts in semiconductor integrated circuits are fabricated by formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

摘要翻译： 通过形成通过绝缘层的接触开口来制造半导体集成电路中的层间接触。 一层难熔金属或难熔金属合金沉积在集成电路芯片的表面上。 然后在显着提高的温度下沉积铝层，使得在铝层和难熔金属层之间的界面处形成铝/难熔金属合金。 这种合金的形成导致接触开口内的金属膨胀，从而填充接触开口并为沉积的铝层提供光滑的上部轮廓。

公开(公告)号：US6159836A

公开(公告)日：2000-12-12

申请号：US438099

申请日：1995-05-08

申请人： Che-Chia Wei

发明人： Che-Chia Wei

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable semiconductor contact structure and method are provided. A semiconductor substrate has a first patterned conductive layer for forming an interconnect. A first insulating layer overlies the first patterned conductive layer. An opening is formed through the insulating layer to the first patterned conductive layer to form the contact via. A buffer layer overlies portions of the first insulating layer and covers the opening. A second conductive layer overlies the buffer layer. A third conductive layer then overlies the integrated circuit. The buffer layer is a material, such as amorphous silicon, which functions as an anti-fuse and can be programmed by application of a relatively high programming voltage.

摘要翻译： 提供了可编程半导体接触结构和方法。 半导体衬底具有用于形成互连的第一图案化导电层。 第一绝缘层覆盖在第一图案化导电层上。 通过绝缘层形成开口到第一图案化导电层以形成接触通孔。 缓冲层覆盖第一绝缘层的部分并覆盖开口。 第二导电层覆盖缓冲层。 然后第三导电层覆盖集成电路。 缓冲层是诸如非晶硅的材料，其用作抗熔丝并且可以通过应用相对高的编程电压进行编程。

公开(公告)号：US5500382A

公开(公告)日：1996-03-19

申请号：US293140

申请日：1994-08-19

申请人： Che-Chia Wei

发明人： Che-Chia Wei

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC分类号： H01L21/76897

摘要： A method for forming a self-aligned contact utilizes a thin insulating layer formed on the upper surface of a conductive layer. A barrier layer is deposited over the insulating layer, and gate electrodes are then defined. Sidewall spacers are formed along the vertical sidewalls of the gate electrodes. During formation of the sidewall spacers the barrier layer protects the gate electrodes. A second insulating layer is then deposited and a via is opened to the substrate. A contact can now be created by depositing conductive material into the via.

摘要翻译： 用于形成自对准接触的方法利用形成在导电层的上表面上的薄绝缘层。 在绝缘层上沉积阻挡层，然后限定栅电极。 沿着栅电极的垂直侧壁形成侧壁间隔物。 在形成侧壁间隔物期间，阻挡层保护栅电极。 然后沉积第二绝缘层，并且通孔向基板开口。 现在可以通过将导电材料沉积到通孔中来形成接触。

公开(公告)号：US5326724A

公开(公告)日：1994-07-05

申请号：US815312

申请日：1991-12-27

申请人： Che-Chia Wei

发明人： Che-Chia Wei

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/306 ,  H01L21/336 ,  H01L29/78 ,  H01L21/283 ,  H01L21/31

CPC分类号： H01L21/28518 ,  Y10S148/015 ,  Y10S148/019 ,  Y10S438/902 ,  Y10S438/97

摘要： A titanium nitride layer is deposited between the metal titanium layer and the oxide cap of a conventional oxide capped titanium disilicide technology process. This titanium nitride layer is deposited in-situ after a certain thickness of metal titanium has been deposited by bleeding nitrogen gas into the titanium sputter machine. Thereafter the normal oxide cap is deposited over this titanium nitride layer. The normal titanium react process is performed to produce titanium disilicide. After the titanium disilicide has been produced, it is then necessary to strip off the oxide cap. The extra titanium nitride layer makes it is possible to use a wet etch to remove the oxide cap, with the titanium nitride layer serving as a etch stop. In this manner an isotropic wet etch may be employed to remove all of the oxide cap layer. The isotropic wet etch is preferably a 10% buffered HF etch.

摘要翻译： 在常规氧化物封端的二硅化钛工艺工艺的金属钛层和氧化物盖之间沉积氮化钛层。 在通过将氮气渗入钛溅射机中沉积了一定厚度的金属钛之后，该氮化钛层原位沉积。 此后，在该氮化钛层上沉积正常氧化物盖。 进行正常的钛反应工艺以生产二硅化钛。 在制造二硅化钛后，需要剥离氧化物盖。 额外的氮化钛层使得可以使用湿蚀刻去除氧化物盖，其中氮化钛层用作蚀刻停止。 以这种方式，可以采用各向同性的湿蚀刻来去除所有氧化物盖层。 各向同性湿蚀刻优选为10％缓冲的HF蚀刻。

公开(公告)号：US5317192A

公开(公告)日：1994-05-31

申请号：US879190

申请日：1992-05-06

申请人： Fusen E. Chen ,  Girish A. Dixit ,  Che-Chia Wei

发明人： Fusen E. Chen ,  Girish A. Dixit ,  Che-Chia Wei

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/400

CPC分类号： H01L23/5226 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

摘要： A method is provided for forming an integrated circuit contact structure. A conductive region is formed on a semiconductor device. Thereafter an insulating layer is formed over the conductive region. An opening is then formed through the insulating region to the conductive region. A thin barrier layer is deposited over the integrated circuit contact structure. A portion of the thin barrier layer is removed by backsputtering the integrated circuit contact structure so that only a thin barrier sidewall remains. Finally, a conductive metal layer is deposited over the integrated circuit contact structure. In one embodiment, the integrated circuit contact structure is baked before the conductive metal layer is deposited.

摘要翻译： 提供了一种用于形成集成电路接触结构的方法。 在半导体器件上形成导电区域。 此后，在导电区域上形成绝缘层。 然后通过绝缘区域形成到导电区域的开口。 薄的势垒层沉积在集成电路接触结构上。 通过反向溅射集成电路接触结构来去除薄势垒层的一部分，使得只有薄的阻挡侧壁保留。 最后，在集成电路接触结构上沉积导电金属层。 在一个实施例中，在沉积导电金属层之前烘烤集成电路接触结构。

公开(公告)号：US5246883A

公开(公告)日：1993-09-21

申请号：US832088

申请日：1992-02-06

申请人： Yih-Shung Lin ,  Lun-Tseng Lu ,  Fu-Tai Liou ,  Che-Chia Wei ,  John L. Walters

发明人： Yih-Shung Lin ,  Lun-Tseng Lu ,  Fu-Tai Liou ,  Che-Chia Wei ,  John L. Walters

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L2924/0002

摘要： A method is provided for forming contact vias in an integrated circuit. Initially, a first buffer layer is formed over an insulating layer in an integrated circuit. The first buffer layer has a different etch rate from the insulating layer. A second buffer layer is then formed over the first buffer layer, with the second buffer layer having an etch rate which is faster than the first buffer layer. An isotropic etch is performed to create an opening through the second buffer layer and a portion of the first buffer layer. Because the second buffer layer etches faster than the first buffer layer, the slant of the sideswalls of the opening can be controlled. An anisotropic etch is then performed to complete formation of the contact via.

公开(公告)号：US4788160A

公开(公告)日：1988-11-29

申请号：US32836

申请日：1987-03-31

申请人： Robert H. Havemann ,  Roger A. Haken ,  Thomas E. Tang ,  Che-Chia Wei

发明人： Robert H. Havemann ,  Roger A. Haken ,  Thomas E. Tang ,  Che-Chia Wei

IPC分类号： H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L29/456 ,  Y10S148/105 ,  Y10S148/147 ,  Y10S438/923

摘要： A process for forming shallow silicided junctions includes the step of sputtering a layer of titanium (28) over a moat region to cover a gate electrode (18) and a sidewall oxide (22) formed on the sidewalls of the gate electrode (18). The titanium is reacted with exposed silicon regions (24) and (26) to form silicide layers (30) and (32) and then dopant impurities are implanted into the substrate (10) prior to stripping the unreacted titanium. The unreacted titanium (36), (38), or (40) functions as a mask to both offset the implanted regions from the channel region (20) under the gate electrode (18) and also to prevent impurities from entering the substrate at regions outside the defined moat region.

摘要翻译： 形成浅硅化物结的方法包括在护城河区域上溅射钛（28）层以覆盖形成在栅电极（18）的侧壁上的栅电极（18）和侧壁氧化物（22）的步骤。 钛与暴露的硅区（24）和（26）反应以形成硅化物层（30）和（32），然后在汽提未反应的钛之前将掺杂剂杂质注入到衬底（10）中。 未反应的钛（36），（38）或（40）起到掩模的作用，以将注入区域从栅电极（18）下方的沟道区域（20）偏移，并且还防止杂质在区域 在定义的护城河地区之外。

公开(公告)号：US06313034B1

公开(公告)日：2001-11-06

申请号：US08510765

申请日：1995-08-03

申请人： Yang Pan ,  Che-Chia Wei

发明人： Yang Pan ,  Che-Chia Wei

IPC分类号： H01L2128

CPC分类号： H01L21/823418 ,  H01L21/76202 ,  H01L21/823468 ,  H01L21/823481

摘要： A method for forming integrated circuit device structures upon active semiconductor regions of a semiconductor substrate. The active semiconductor regions are defined by Field OXide (FOX) isolation regions which are formed through a Polysilicon Buffered LOCal Oxidation of Silicon (PBLOCOS) oxidation mask structure. The PBLOCOS oxidation mask structure includes a blanket pad oxide layer which resides upon the semiconductor substrate, a blanket polysilicon buffer layer which resides upon the blanket pad oxide layer and a patterned silicon nitride layer which resides upon the blanket polysilicon buffer layer. Portions of the blanket polysilicon buffer layer and the blanket pad oxide layer exposed through the patterned silicon nitride layer are completely consumed to leave remaining the patterned silicon nitride layer, a patterned polysilicon buffer layer and a patterned pad oxide layer upon the active regions of the semiconductor substrate which are separated by the FOX isolation regions. The portions of the patterned silicon nitride layer, the patterned polysilicon buffer layer and the patterned pad oxide layer are employed in forming integrated circuit device structures upon the active semiconductor region of the semiconductor substrate.

摘要翻译： 一种用于在半导体衬底的有源半导体区域上形成集成电路器件结构的方法。 活性半导体区域由通过硅（PBLOCOS）氧化掩模结构的多晶硅缓冲局部氧化形成的场OXide（FOX）隔离区限定。 PBLOCOS氧化掩模结构包括位于半导体衬底上的覆盖层氧化物层，驻留在覆盖层氧化物层上的覆盖多晶硅缓冲层和驻留在覆盖多晶硅缓冲层上的图案化氮化硅层。 通过图案化氮化硅层暴露的覆盖多晶硅缓冲层和覆盖层氧化物层的部分被完全消耗以留下图案化的氮化硅层，在半导体的有源区上留下图案化的多晶硅缓冲层和图案化的衬垫氧化物层 由FOX隔离区隔开的衬底。 图案化氮化硅层，图案化多晶硅缓冲层和图案化衬垫氧化物层的部分用于在半导体衬底的有源半导体区域上形成集成电路器件结构。

公开(公告)号：US5977607A

公开(公告)日：1999-11-02

申请号：US447362

申请日：1995-05-23

申请人： Robert Louis Hodges ,  Frank Randolph Bryant ,  Fusen E. Chen ,  Che-Chia Wei

发明人： Robert Louis Hodges ,  Frank Randolph Bryant ,  Fusen E. Chen ,  Che-Chia Wei

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L29/00

CPC分类号： H01L21/32 ,  H01L21/76202

摘要： A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.

摘要翻译： 提供一种用于形成集成电路的隔离氧化物区域的方法和根据该集成电路形成的集成电路。 在衬底的一部分上形成衬垫氧化物层。 在衬垫氧化物层上形成第一氮化硅层。 然后在第一氮化硅层上形成多晶硅缓冲层。 在多晶硅层上形成第二氮化硅层。 在第二氮化硅层上形成并图案化光致抗蚀剂层。 通过第二氮化硅层和多晶硅缓冲层蚀刻开口以暴露第一氮化硅层的一部分。 至少在开口中暴露的多晶硅缓冲层上形成第三氮化硅区域。 在开口中蚀刻第一氮化硅层。 然后在开口中形成场氧化物区域。