公开(公告)号：US07825713B2

公开(公告)日：2010-11-02

申请号：US12286765

申请日：2008-10-02

申请人： Chen-Yi Lee ,  Jui-Yuan Yu ,  Chien-Ying Yu ,  Juinn-Ting Chen

发明人： Chen-Yi Lee ,  Jui-Yuan Yu ,  Chien-Ying Yu ,  Juinn-Ting Chen

IPC分类号： H03H11/26

CPC分类号： G06F1/14

摘要： An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals.

摘要翻译： 绝对时间延迟产生装置包括PVT（过程电压 - 温度）检测装置和延迟定时发生器。 PVT检测装置至少包括延迟模块和信号相位/频率控制模块。 延迟模块包括控制单元和参考单元。 控制单元与PVT的延迟属性的灵敏度不同于参考单元。 延迟模块比较原点信号分别通过控制单元和参考单元产生的相位或频率差，并产生延迟模块的延迟参数。 信号相位/频率控制模块接收并比较延迟参数以确定绝对时间延迟产生装置的环境PVT条件，以便控制和校正延迟定时发生器从而产生精确的绝对时间延迟。 在各种PVT影响下，绝对时间延迟产生装置能够产生精确的绝对时间信号。

公开(公告)号：US20100013536A1

公开(公告)日：2010-01-21

申请号：US12286765

申请日：2008-10-02

申请人： Chen-Yi Lee ,  Jui-Yuan Yu ,  Chien-Ying Yu ,  Juinn-Ting Chen

发明人： Chen-Yi Lee ,  Jui-Yuan Yu ,  Chien-Ying Yu ,  Juinn-Ting Chen

IPC分类号： H03H11/26

CPC分类号： G06F1/14

摘要： An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals.

公开(公告)号：US07924100B2

公开(公告)日：2011-04-12

申请号：US12180176

申请日：2008-07-25

申请人： Chen-Yi Lee ,  Jui-Yuan Yu

发明人： Chen-Yi Lee ,  Jui-Yuan Yu

IPC分类号： G01R23/00

CPC分类号： H03J7/04

摘要： A communication device uses a local clock generator to regenerate the carrier frequency of the reference signal from a remote communication. In particular, a closed loop is used to self-calibrate the local pulse till the frequency is fixed to be within a fixed frequency margin. Once the local pulse is obtained, the demodulator will use the local pulse to demodulate the reference signal to generate the data signal.

摘要翻译： 通信设备使用本地时钟发生器从远程通信重新生成参考信号的载波频率。 特别地，闭环用于自校准本地脉冲，直到频率固定在固定的频率范围内。 一旦获得本地脉冲，解调器将使用本地脉冲来解调参考信号以产生数据信号。

公开(公告)号：US20090278617A1

公开(公告)日：2009-11-12

申请号：US12180176

申请日：2008-07-25

申请人： Chen-Yi Lee ,  Jui-Yuan Yu

发明人： Chen-Yi Lee ,  Jui-Yuan Yu

IPC分类号： G01R23/00 ,  H03J7/04

CPC分类号： H03J7/04

摘要： This invention discloses a crystal-less communication device and self-calibrated embedded virtual crystal clock generation method. In communication systems, the invention proposes a crystal-less scheme in the device for wireless or wired-line communications. The operation concepts are that the transmitter Device-1 provides Device-2 a reference signal, and Device-2 takes this signal to generate a local signal with the similar frequency that has limited frequency error compared with the one from Device-1. This invention is done via the circuit-design methodology, so it can be implemented from any kinds of circuit implementation processes, especially the CMOS process. As a result, the hardware can be designed in the way of highly integration and extremely low cost. Also, this can largely change and improve existing communications design architecture, hardware cost, and hardware area.

摘要翻译： 本发明公开了一种无晶体通信装置和自校准嵌入式虚拟晶体钟产生方法。 在通信系统中，本发明提出了一种无线或有线通信设备中的无晶体方案。 操作原理是发射机Device-1向Device-2提供参考信号，Device-2采用该信号产生与Device-1相比具有有限频率误差相似频率​​的本地信号。 本发明通过电路设计方法完成，因此可以通过任何种类的电路实现过程，特别是CMOS工艺实现。 因此，硬件可以以高集成度和极低成本的方式进行设计。 此外，这可以大大改变和改进现有的通信设计架构，硬件成本和硬件领域。

公开(公告)号：US08466729B2

公开(公告)日：2013-06-18

申请号：US13352350

申请日：2012-01-18

申请人： Chen-Yi Lee ,  Chien-Ying Yu ,  Chia-Jung Yu

发明人： Chen-Yi Lee ,  Chien-Ying Yu ,  Chia-Jung Yu

IPC分类号： H03H11/26

CPC分类号： H03L7/0997

摘要： A delay cell includes a first inverted transistor pair, a second inverted transistor pair and a plurality of delay units. The first inverted transistor pair is used to receive an input signal. The second inverted transistor pair is electrically cross-coupled to the first inverted transistor pair and cross-controlled by the first inverted transistor pair. The delay units are cascaded between the first inverted transistor pair and between the second inverted transistor pair, thereby providing a plurality of signal propagation delays sequentially, wherein the input signal is delayed for a pre-determined time by the first inverted transistor pair, the second inverted transistor pair and the delay units which are operated sequentially, thereby creating an output signal corresponding to the pre-determined time. A digitally controlled oscillator including the aforementioned delay cells is provided.

摘要翻译： 延迟单元包括第一反相晶体管对，第二反相晶体管对和多个延迟单元。 第一反相晶体管对用于接收输入信号。 第二反相晶体管对与第一反相晶体管对电交叉耦合并由第一反相晶体管对交叉控制。 延迟单元在第一反相晶体管对之间和第二反向晶体管对之间级联，从而依次提供多个信号传播延迟，其中输入信号被第一反相晶体管对延迟预定时间，第二 反相晶体管对和延迟单元，从而产生与预定时间对应的输出信号。 提供了包括上述延迟单元的数字控制振荡器。

公开(公告)号：US09048259B2

公开(公告)日：2015-06-02

申请号：US13562805

申请日：2012-07-31

申请人： Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

发明人： Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L21/76202 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

摘要翻译： 半导体结构包括具有第一部分和第二部分的半导体衬底。 第一Fin场效应晶体管（FinFET）形成在半导体衬底的第一部分上，其中第一FinFET包括具有第一鳍片高度的第一鳍片。 第二FinFET形成在半导体衬底的第二部分上，其中第二FinFET包括具有不同于第一鳍片高度的第二鳍片高度的第二鳍片。 第一翅片的顶表面基本上与第二翅片的顶表面平齐。 穿通止动件位于第一FinFET的下面并邻接，其中穿通止动件将第一鳍片与半导体衬底的第一部分隔离。

公开(公告)号：USD722382S1

公开(公告)日：2015-02-10

申请号：US29444570

申请日：2013-01-31

申请人： Chen-Yi Lee ,  Hao-Husan Huang

设计人： Chen-Yi Lee ,  Hao-Husan Huang

公开(公告)号：US08943391B2

公开(公告)日：2015-01-27

申请号：US13609829

申请日：2012-09-11

申请人： Yi-Min Lin ,  Chih-Hsiang Hsu ,  Hsie-Chia Chang ,  Chen-Yi Lee

发明人： Yi-Min Lin ,  Chih-Hsiang Hsu ,  Hsie-Chia Chang ,  Chen-Yi Lee

IPC分类号： H03M13/00 ,  H03M13/15 ,  H03M13/45

CPC分类号： H03M13/152 ,  H03M13/1525 ,  H03M13/159 ,  H03M13/451 ,  H03M13/6502

摘要： In a cyclic code decoding method, a decoder analyzes a received codeword to identify unreliable symbols in the codeword, and sets candidate syndrome patterns accordingly. Then, a syndrome calculator calculates evaluated syndrome values associated with one of the candidate syndrome patterns, and an error location polynomial (ELP) generator generates an ELP according to the syndrome values. An error correction device corrects the errors in the codeword according to the ELP when a degree of the ELP is not more than a threshold value, and the syndrome calculator adjusts the syndrome values and the ELP generator generates another ELP according to the adjusted syndrome values when otherwise.

摘要翻译： 在循环码解码方法中，解码器分析接收的码字以识别码字中的不可靠符号，并相应地设置候选综合征模式。 然后，校正子计算器计算与候选校正子模式中的一个相关联的评估校正子值，并且错误位置多项式（ELP）生成器根据校正子值生成ELP。 当ELP的程度不大于阈值时，错误校正装置根据ELP校正码字中的错误，并且校正子计算器调整校正子值，并且ELP生成器根据校正的校正子值生成另一ELP， 除此以外。

公开(公告)号：US20120299110A1

公开(公告)日：2012-11-29

申请号：US13562805

申请日：2012-07-31

申请人： Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

发明人： Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC分类号： H01L27/088

CPC分类号： H01L21/76202 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

摘要翻译： 半导体结构包括具有第一部分和第二部分的半导体衬底。 第一Fin场效应晶体管（FinFET）形成在半导体衬底的第一部分上，其中第一FinFET包括具有第一鳍片高度的第一鳍片。 第二FinFET形成在半导体衬底的第二部分上，其中第二FinFET包括具有不同于第一鳍片高度的第二鳍片高度的第二鳍片。 第一翅片的顶表面基本上与第二翅片的顶表面平齐。 穿通止动件位于第一FinFET的下面并邻接，其中穿通止动件将第一鳍片与半导体衬底的第一部分隔离。

公开(公告)号：US08108762B2

公开(公告)日：2012-01-31

申请号：US11939119

申请日：2007-11-13

申请人： Chih-Hao Liu ,  Yen-Chin Liao ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

发明人： Chih-Hao Liu ,  Yen-Chin Liao ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： H03M13/1137 ,  H03M13/1114 ,  H03M13/658 ,  H03M13/6591

摘要： An operating method and a circuit for low density parity check (LDPC) decoders, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the difference between the newly generated check messages and the previous check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. The required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.

摘要翻译： 一种用于低密度奇偶校验（LDPC）解码器的操作方法和电路，其中将原始比特节点并入校验节点用于同时操作。 根据新生成的检查消息和先前检查节点消息之间的差异来生成位节点消息。 可以立即更新位节点消息，并且可以提高解码器吞吐量。 可以有效地减少LDPC解码器所需的存储器，并且还可以提高解码速度。