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    Method and Apparatus for Signal Formation with Guaranteed Consistent Overhead Insertion
    1.
    发明申请
    Method and Apparatus for Signal Formation with Guaranteed Consistent Overhead Insertion 有权
    用于信号形成的方法和装置，保证一致的开销插入

    公开(公告)号：US20100329673A1

    公开(公告)日：2010-12-30

    申请号：US12494449

    申请日：2009-06-30

    申请人： Cheng Gang Duan ,  Lin Hua ,  Ze Mian Huang ,  Michael S. Shaffer ,  Tao Wang

    发明人： Cheng Gang Duan ,  Lin Hua ,  Ze Mian Huang ,  Michael S. Shaffer ,  Tao Wang

    IPC分类号： H04J14/00

    CPC分类号： H04J3/04 ,  H04J3/1611

    摘要： A communication device comprises a signal combiner, first storage elements, second storage elements and a controller. The signal combiner is configured to combine overhead information with additional information in forming a frame of a signal. The first storage elements are adapted to receive respective portions of a given block of the overhead information to be applied to the signal combiner, and the second storage elements are coupled between respective ones of the first storage elements and respective inputs of the signal combiner. The controller is operative to monitor a count of portions of the frame as the frame is formed by the signal combiner and to control loading of the portions of the given block of the overhead information into the second storage elements from the first storage elements responsive to the monitored count. The disclosed techniques for guaranteed consistent overhead insertion can be implemented in any type of communication system which utilizes overhead insertion in its framing operations.

    摘要翻译： 通信设备包括信号组合器，第一存储元件，第二存储元件和控制器。 信号组合器被配置为将开销信息与形成信号的帧的附加信息组合。 第一存储元件适于接收要施加到信号组合器的开销信息的给定块的相应部分，并且第二存储元件耦合在信号组合器的相应的第一存储元件和相应的输入端之间。 所述控制器可操作以在所述帧由所述信号组合器形成时监视所述帧的部分的计数，并且响应于所述第一存储元件控制所述开销信息的给定块的所述部分的部分到所述第二存储元件 监测数。 所公开的用于保证一致的开销插入的技术可以在任何类型的通信系统中实现，该系统在其成帧操作中利用开销插入。

    Method and apparatus for signal formation with guaranteed consistent overhead insertion
    2.
    发明授权
    Method and apparatus for signal formation with guaranteed consistent overhead insertion 有权
    用于信号形成的方法和装置，保证一致的开销插入

    公开(公告)号：US08249063B2

    公开(公告)日：2012-08-21

    申请号：US12494449

    申请日：2009-06-30

    申请人： Cheng Gang Duan ,  Lin Hua ,  Ze Mian Huang ,  Michael S. Shaffer ,  Tao Wang

    发明人： Cheng Gang Duan ,  Lin Hua ,  Ze Mian Huang ,  Michael S. Shaffer ,  Tao Wang

    IPC分类号： H04L12/50 ,  H04Q11/00

    CPC分类号： H04J3/04 ,  H04J3/1611

    摘要： A communication device comprises a signal combiner, first storage elements, second storage elements and a controller. The signal combiner is configured to combine overhead information with additional information in forming a frame of a signal. The first storage elements are adapted to receive respective portions of a given block of the overhead information to be applied to the signal combiner, and the second storage elements are coupled between respective ones of the first storage elements and respective inputs of the signal combiner. The controller is operative to monitor a count of portions of the frame as the frame is formed by the signal combiner and to control loading of the portions of the given block of the overhead information into the second storage elements from the first storage elements responsive to the monitored count. The disclosed techniques for guaranteed consistent overhead insertion can be implemented in any type of communication system which utilizes overhead insertion in its framing operations.

    摘要翻译： 通信设备包括信号组合器，第一存储元件，第二存储元件和控制器。 信号组合器被配置为将开销信息与形成信号的帧的附加信息组合。 第一存储元件适于接收要施加到信号组合器的开销信息的给定块的相应部分，并且第二存储元件耦合在信号组合器的相应的第一存储元件和相应的输入端之间。 所述控制器可操作以在所述帧由所述信号组合器形成时监视所述帧的部分的计数，并且响应于所述第一存储元件控制所述开销信息的给定块的所述部分的部分到所述第二存储元件 监测数。 所公开的用于保证一致的开销插入的技术可以在任何类型的通信系统中实现，该系统在其成帧操作中利用开销插入。

    METHODS AND APPARATUS FOR SYSTEM FRAMING SYNCHRONIZATION CONTROL FOR A FRAMER/MAPPER/MULTIPLEXOR DEVICE WITH 1+1 AND EQUIPMENT PROTECTION
    3.
    发明申请
    METHODS AND APPARATUS FOR SYSTEM FRAMING SYNCHRONIZATION CONTROL FOR A FRAMER/MAPPER/MULTIPLEXOR DEVICE WITH 1+1 AND EQUIPMENT PROTECTION 有权
    用于具有1 + 1和设备保护的框架/映射器/多路复用器件的系统框架同步控制的方法和装置

    公开(公告)号：US20100221001A1

    公开(公告)日：2010-09-02

    申请号：US12394270

    申请日：2009-02-27

    申请人： Cheng Gang Duan ,  Lin Hua ,  Michael S. Shaffer ,  Tao Wang ,  Qian G. Xu

    发明人： Cheng Gang Duan ,  Lin Hua ,  Michael S. Shaffer ,  Tao Wang ,  Qian G. Xu

    IPC分类号： H04J14/00

    CPC分类号： H04J3/14 ,  H04J3/0623 ,  H04J3/0685 ,  H04J2203/006

    摘要： Methods and apparatus are provided for framing synchronization control for a framer/mapper/multiplexor (FMM) device with 1+1 and equipment protection. FMM device are disclosed that synchronize one or more internal signals by changing a phase of the one or more internal signals without changing a frequency of the one or more internal signals based on a desired phase at a destination of each of the one or more internal signals. A programmable synchronization signal may optionally be employed for the synchronization.

    摘要翻译： 提供了用于具有1 + 1和设备保护的成帧器/映射/多路复用器（FMM）装置的成帧同步控制的方法和装置。 FMM装置被公开，其通过改变一个或多个内部信号的相位来同步一个或多个内部信号，而不改变一个或多个内部信号的频率，基于在一个或多个内部信号中的每一个的目的地的期望相位 。 可选地可以采用可编程同步信号来进行同步。

    Obtaining channel status in a network-based data transport architecture
    5.
    发明授权
    Obtaining channel status in a network-based data transport architecture 有权
    在基于网络的数据传输架构中获取通道状态

    公开(公告)号：US07830899B2

    公开(公告)日：2010-11-09

    申请号：US11140428

    申请日：2005-05-27

    申请人： Cheng Gang Duan ,  Lin Hua ,  Tao Wang

    发明人： Cheng Gang Duan ,  Lin Hua ,  Tao Wang

    IPC分类号： H04L12/28 ,  H04J3/04

    CPC分类号： H04J3/14 ,  H04L12/43 ,  H04L43/0817

    摘要： A buffer circuit for use in a node in a network-based data transport system is configurable for providing channel status information of all channels associated with a given signal in the network-based data transport system. The buffer circuit includes a memory and a controller coupled to the memory. The controller is operative: (i) to receive channel status information from a plurality of different channel status sources; (ii) to select one of the channel status sources for supplying the channel status information at a given point in time; and (iii) to store the channel status information corresponding to the selected channel status source in the memory.

    摘要翻译： 用于基于网络的数据传输系统中的节点的缓冲电路可配置为在基于网络的数据传输系统中提供与给定信号相关联的所有信道的信道状态信息。 缓冲电路包括存储器和耦合到存储器的控制器。 控制器可操作：（i）从多个不同的信道状态源接收信道状态信息; （ii）选择在给定时间点提供频道状态信息的频道状态来源之一; 和（iii）将与所选择的信道状态源相对应的信道状态信息存储在存储器中。

    Base station timing control using synchronous transport signals
    6.
    发明授权
    Base station timing control using synchronous transport signals 有权
    基站定时控制采用同步传输信号

    公开(公告)号：US09210674B2

    公开(公告)日：2015-12-08

    申请号：US13429606

    申请日：2012-03-26

    申请人： Yifan Lin ,  Ze Mian Huang ,  Tao Wang ,  Lin Sun ,  Hao Li

    发明人： Yifan Lin ,  Ze Mian Huang ,  Tao Wang ,  Lin Sun ,  Hao Li

    IPC分类号： H04W4/00 ,  H04W56/00 ,  H04W92/04

    CPC分类号： H04W56/001 ,  H04W92/045

    摘要： A base station of a wireless system comprises a local clock source and timing circuitry coupled to the local clock source. The timing circuitry is configured to adjust at least one parameter of the local clock source based at least in part on timing information extracted from designated portions of each of one or more frames of a synchronous transport signal received in the base station. The base station may further comprise a physical layer device, such as a mapper, configured to extract the timing information from the designated portions of each of the one or more frames of the synchronous transport signal. The designated portions of the one or more frames of the synchronous transport signal from which the timing information is extracted may comprise designated overhead bytes of the one or more frames, such as, for example, transport overhead (TOH) bytes.

    摘要翻译： 无线系统的基站包括耦合到本地时钟源的本地时钟源和定时电路。 定时电路被配置为至少部分地基于从在基站中接收的同步传输信号的一个或多个帧的每一个的指定部分提取的定时信息来调整本地时钟源的至少一个参数。 基站还可以包括诸如映射器的物理层设备，被配置为从同步传输信号的一个或多个帧中的每一个的指定部分提取定时信息。 提取定时信息的同步传输信号的一个或多个帧的指定部分可以包括一个或多个帧的指定的开销字节，例如传输开销（TOH）字节。

    BASE STATION TIMING CONTROL USING SYNCHRONOUS TRANSPORT SIGNALS
    7.
    发明申请
    BASE STATION TIMING CONTROL USING SYNCHRONOUS TRANSPORT SIGNALS 有权
    使用同步传输信号的基站时序控制

    公开(公告)号：US20130250850A1

    公开(公告)日：2013-09-26

    申请号：US13429606

    申请日：2012-03-26

    申请人： Yifan Lin ,  Ze Mian Huang ,  Tao Wang ,  Lin Sun ,  Hao Li

    发明人： Yifan Lin ,  Ze Mian Huang ,  Tao Wang ,  Lin Sun ,  Hao Li

    IPC分类号： H04W56/00

    CPC分类号： H04W56/001 ,  H04W92/045

    摘要： A base station of a wireless system comprises a local clock source and timing circuitry coupled to the local clock source. The timing circuitry is configured to adjust at least one parameter of the local clock source based at least in part on timing information extracted from designated portions of each of one or more frames of a synchronous transport signal received in the base station. The base station may further comprise a physical layer device, such as a mapper, configured to extract the timing information from the designated portions of each of the one or more frames of the synchronous transport signal. The designated portions of the one or more frames of the synchronous transport signal from which the timing information is extracted may comprise designated overhead bytes of the one or more frames, such as, for example, transport overhead (TOH) bytes.

    摘要翻译： 无线系统的基站包括耦合到本地时钟源的本地时钟源和定时电路。 定时电路被配置为至少部分地基于从在基站中接收的同步传输信号的一个或多个帧的每一个的指定部分提取的定时信息来调整本地时钟源的至少一个参数。 基站还可以包括诸如映射器的物理层设备，被配置为从同步传输信号的一个或多个帧中的每一个的指定部分提取定时信息。 提取定时信息的同步传输信号的一个或多个帧的指定部分可以包括一个或多个帧的指定的开销字节，例如传输开销（TOH）字节。

    Obtaining channel status in a network-based data transport architecture
    8.
    发明申请
    Obtaining channel status in a network-based data transport architecture 有权
    在基于网络的数据传输架构中获取通道状态

    公开(公告)号：US20060268730A1

    公开(公告)日：2006-11-30

    申请号：US11140428

    申请日：2005-05-27

    申请人： Cheng Duan ,  Lin Hua ,  Tao Wang

    发明人： Cheng Duan ,  Lin Hua ,  Tao Wang

    IPC分类号： H04J1/16 ,  H04J3/12

    CPC分类号： H04J3/14 ,  H04L12/43 ,  H04L43/0817

    摘要： A buffer circuit for use in a node in a network-based data transport system is configurable for providing channel status information of all channels associated with a given signal in the network-based data transport system. The buffer circuit includes a memory and a controller coupled to the memory. The controller is the operative: (i) to receive channel status information from a plurality of different channel status sources; (ii) to select one of the channel status sources for supplying the channel status information at a given point in time; and (iii) to store the channel status information corresponding to the selected channel status source in the memory.

    摘要翻译： 用于基于网络的数据传输系统中的节点的缓冲电路可配置为在基于网络的数据传输系统中提供与给定信号相关联的所有信道的信道状态信息。 缓冲电路包括存储器和耦合到存储器的控制器。 控制器是可操作的：（i）从多个不同的信道状态源接收信道状态信息; （ii）选择在给定时间点提供频道状态信息的频道状态来源之一; 和（iii）将与所选择的信道状态源相对应的信道状态信息存储在存储器中。