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    Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints
    2.
    发明授权
    Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints 有权
    用于动态二进制转换器的装置和方法，以最小的优化约束来支持精确异常

    公开(公告)号：US07757221B2

    公开(公告)日：2010-07-13

    申请号：US11241610

    申请日：2005-09-30

    申请人： Bixia Zheng ,  Cheng C. Wang ,  Ho-seop Kim ,  Mauricio Breternitz, Jr. ,  Youfeng Wu

    发明人： Bixia Zheng ,  Cheng C. Wang ,  Ho-seop Kim ,  Mauricio Breternitz, Jr. ,  Youfeng Wu

    IPC分类号： G06F9/45

    CPC分类号： G06F9/45516 ,  G06F8/443

    摘要： A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.

    摘要翻译： 一种用于动态二进制转换器的方法和装置，以最小的优化约束来支持精确的异常。 在一个实施例中，该方法包括将源指令集架构（ISA）生成的源二进制应用程序转换为源二进制应用程序的顺序中间表示（IR）。 在一个实施例中，顺序IR被修改为包含从源二进制应用程序识别的每个异常指令的异常恢复信息，以使动态二进制转换器（DBT）能够将异常恢复值表示为由IR指令使用的常规值。 在一个实施例中，可以对异常指令向下移动通过不可逆指令以形成非顺序IR的限制来优化顺序IR。 在一个实施例中，非顺序IR被优化以形成目标ISA的翻译二进制应用程序。 描述和要求保护其他实施例。

    Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints
    4.
    发明申请
    Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints 有权
    用于动态二进制转换器的装置和方法，以最小的优化约束来支持精确异常

    公开(公告)号：US20070079304A1

    公开(公告)日：2007-04-05

    申请号：US11241610

    申请日：2005-09-30

    申请人： Bixia Zheng ,  Cheng Wang ,  Ho-seop Kim ,  Mauricio Breternitz ,  Youfeng Wu

    发明人： Bixia Zheng ,  Cheng Wang ,  Ho-seop Kim ,  Mauricio Breternitz ,  Youfeng Wu

    IPC分类号： G06F9/45

    CPC分类号： G06F9/45516 ,  G06F8/443

    摘要： A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.

    摘要翻译： 一种用于动态二进制转换器的方法和装置，以最小的优化约束来支持精确的异常。 在一个实施例中，该方法包括将源指令集架构（ISA）生成的源二进制应用程序转换为源二进制应用程序的顺序中间表示（IR）。 在一个实施例中，顺序IR被修改为包含从源二进制应用程序识别的每个异常指令的异常恢复信息，以使动态二进制转换器（DBT）能够将异常恢复值表示为由IR指令使用的常规值。 在一个实施例中，可以对异常指令向下移动通过不可逆指令以形成非顺序IR的限制来优化顺序IR。 在一个实施例中，非顺序IR被优化以形成目标ISA的翻译二进制应用程序。 描述和要求保护其他实施例。

    ON-DEMAND EMULATION VIA USER-LEVEL EXCEPTION HANDLING
    5.
    发明申请
    ON-DEMAND EMULATION VIA USER-LEVEL EXCEPTION HANDLING 有权
    通过用户级别异常处理实现仿真

    公开(公告)号：US20090172713A1

    公开(公告)日：2009-07-02

    申请号：US11968055

    申请日：2007-12-31

    申请人： Ho-Seop Kim ,  Mauricio Breternitz, JR. ,  Youfeng Wu

    发明人： Ho-Seop Kim ,  Mauricio Breternitz, JR. ,  Youfeng Wu

    IPC分类号： G06F9/54 ,  G06F9/302

    CPC分类号： G06F9/30145 ,  G06F9/4552

    摘要： Methods and apparatuses enable on-demand instruction emulation via user-level exception handling. A non-supported instruction triggers an exception during runtime of a program. In response to the exception, a user-level or application-level exception handler is launched, instead of a kernel-level handler. Then the exception handler can execute at the application layer instead of the kernel level. The handler identifies the instruction and emulates the instruction, where emulation of the instruction is supported by the handler. Emulating the instructions enables the program to continue execution. Repeated instruction emulation is amortized via dynamic binary translation of hot code.

    摘要翻译： 方法和设备通过用户级异常处理实现按需指令仿真。 不支持的指令在程序运行时触发异常。 响应于异常，启动用户级或应用程序级异常处理程序，而不是内核级处理程序。 然后异常处理程序可以在应用程序层而不是内核级别执行。 处理程序标识指令并模拟指令，其中指令的仿真由处理程序支持。 仿真指令使程序能够继续执行。 重复的指令仿真通过热代码的动态二进制转换进行分摊。

    On-demand emulation via user-level exception handling
    6.
    发明授权
    On-demand emulation via user-level exception handling 有权
    通过用户级异常处理进行按需仿真

    公开(公告)号：US08146106B2

    公开(公告)日：2012-03-27

    申请号：US11968055

    申请日：2007-12-31

    申请人： Ho-Seop Kim ,  Mauricio Breternitz, Jr. ,  Youfeng Wu

    发明人： Ho-Seop Kim ,  Mauricio Breternitz, Jr. ,  Youfeng Wu

    IPC分类号： G06F9/44 ,  G06F9/45 ,  G06F9/455

    CPC分类号： G06F9/30145 ,  G06F9/4552

    摘要： Methods and apparatuses enable on-demand instruction emulation via user-level exception handling. A non-supported instruction triggers an exception during runtime of a program. In response to the exception, a user-level or application-level exception handler is launched, instead of a kernel-level handler. Then the exception handler can execute at the application layer instead of the kernel level. The handler identifies the instruction and emulates the instruction, where emulation of the instruction is supported by the handler. Emulating the instructions enables the program to continue execution. Repeated instruction emulation is amortized via dynamic binary translation of hot code.

    摘要翻译： 方法和设备通过用户级异常处理实现按需指令仿真。 不支持的指令在程序运行时触发异常。 响应于异常，启动用户级或应用程序级异常处理程序，而不是内核级处理程序。 然后异常处理程序可以在应用程序层而不是内核级别执行。 处理程序标识指令并模拟指令，其中指令的仿真由处理程序支持。 仿真指令使程序能够继续执行。 重复的指令仿真通过热代码的动态二进制转换进行分摊。

    APPARATUS, METHOD, AND SYSTEM FOR PROVIDING A DECISION MECHANISM FOR CONDITIONAL COMMITS IN AN ATOMIC REGION
    8.
    发明申请
    APPARATUS, METHOD, AND SYSTEM FOR PROVIDING A DECISION MECHANISM FOR CONDITIONAL COMMITS IN AN ATOMIC REGION 有权
    设备，方法和系统，用于提供原子地区条件性的决策机制

    公开(公告)号：US20130318507A1

    公开(公告)日：2013-11-28

    申请号：US13893238

    申请日：2013-05-13

    申请人： Mauricio Breternitz, JR. ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

    发明人： Mauricio Breternitz, JR. ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

    IPC分类号： G06F11/36

    CPC分类号： G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

    摘要： An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

    摘要翻译： 本文描述了用于有条件地提交和/或推测性检查点事务的装置和方法，这可能导致事务的动态调整大小。 在二进制代码的动态优化期间，插入事务以提供内存排序保护措施，这使得动态优化器能够更积极地优化代码。 并且条件提交可以有效地执行动态优化代码，同时尝试防止事务用尽硬件资源。 虽然投机检查点能够在中止交易后快速有效地恢复。 处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。 并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。

    APPARATUS, METHOD, AND SYSTEM FOR PROVIDING A DECISION MECHANISM FOR CONDITIONAL COMMITS IN AN ATOMIC REGION
    10.
    发明申请
    APPARATUS, METHOD, AND SYSTEM FOR PROVIDING A DECISION MECHANISM FOR CONDITIONAL COMMITS IN AN ATOMIC REGION 有权
    设备，方法和系统，用于提供原子地区条件性的决策机制

    公开(公告)号：US20120079246A1

    公开(公告)日：2012-03-29

    申请号：US12890639

    申请日：2010-09-25

    申请人： Mauricio Breternitz, JR. ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

    发明人： Mauricio Breternitz, JR. ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

    IPC分类号： G06F9/30 ,  G06F9/44 ,  G06F15/00

    CPC分类号： G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

    摘要： An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

    摘要翻译： 本文描述了用于有条件地提交/推测的检查点事务的装置和方法，这可能导致事务的动态调整大小。 在二进制代码的动态优化期间，插入事务以提供存储器排序保护措施，这使得动态优化器能够更积极地优化代码。 并且条件提交可以有效地执行动态优化代码，同时尝试防止事务用尽硬件资源。 虽然投机检查点能够在中止交易后快速有效地恢复。 处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。 并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。