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    Semiconductor device and method thereof
    2.
    发明申请
    Semiconductor device and method thereof 审中-公开
    半导体装置及其方法

    公开(公告)号：US20060263971A1

    公开(公告)日：2006-11-23

    申请号：US11436582

    申请日：2006-05-19

    申请人： Kwang-Wook Lee ,  Cheol-Woo Park ,  Yong-Sun Ko ,  Byoung-Moon Yoon ,  Kyung-Hyun Kim

    发明人： Kwang-Wook Lee ,  Cheol-Woo Park ,  Yong-Sun Ko ,  Byoung-Moon Yoon ,  Kyung-Hyun Kim

    IPC分类号： B32B3/10 ,  B32B3/00 ,  H01L21/8244 ,  H01L29/94

    CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  Y10T428/24273 ,  Y10T428/24479

    摘要： A semiconductor device and a method thereof are disclosed. In the example method, a mold layer having an opening may be formed on a substrate. A conductive etchable pattern (e.g., a preliminary conductive pattern, a lower electrode pattern, etc.) may be formed within the opening. The mold layer may be reduced so as to expose a portion of the conductive etchable pattern and less than all of the exposed portion of the conductive etchable pattern may be etched such that the etched conductive etchable pattern has a reduced thickness. The example semiconductor device may include the etched conductive etchable pattern as above-described with respect to the example method.

    摘要翻译： 公开了一种半导体器件及其方法。 在示例性方法中，可以在基板上形成具有开口的模具层。 可以在开口内形成导电刻蚀图案（例如，初步导电图案，下电极图案等）。 可以减小模具层，以便露出导电可蚀刻图案的一部分，并且可以蚀刻少于导电可蚀刻图案的全部暴露部分，使得蚀刻的导电可蚀刻图案具有减小的厚度。 示例性半导体器件可以包括如上面关于示例性方法的蚀刻的导电可蚀刻图案。

    Organic stripping composition and method of etching oxide using the same
    7.
    发明授权
    Organic stripping composition and method of etching oxide using the same 失效
    有机剥离组合物和使用其的氧化物蚀刻方法

    公开(公告)号：US07105474B2

    公开(公告)日：2006-09-12

    申请号：US10634880

    申请日：2003-08-06

    申请人： Tae-Hyun Kim ,  Byoung-Moon Yoon ,  Kyung-Hyun Kim ,  Chang-Lyong Song ,  Yong-Sun Ko

    发明人： Tae-Hyun Kim ,  Byoung-Moon Yoon ,  Kyung-Hyun Kim ,  Chang-Lyong Song ,  Yong-Sun Ko

    IPC分类号： C11D7/50

    CPC分类号： C11D11/0047 ,  C11D3/3942 ,  C11D3/3947 ,  C11D7/06 ,  C11D7/08 ,  C11D7/265 ,  C11D7/28

    摘要： Disclosed is an organic stripping composition and a method of etching a semiconductor device in which the generation of an Si pitting phenomenon can be prevented. The composition includes a compound including a hydroxyl ion (OH−), a compound including a fluorine ion (F−) and a sufficient amount of an oxidizing agent to control the pH of the composition within the range of from about 6.5 to about 8.0. The method includes dry etching an oxide by a dry etching using a plasma, and then ashing the etched oxide using an ashing process to remove an organic material. The method further includes supplying the organic stripping composition to remove residues including any residual organic material, a metal polymer, and an oxide type polymer. The stripping composition is stable onto various metals and does not induce the Si pitting phenomenon.

    摘要翻译： 公开了一种有机剥离组合物和蚀刻半导体器件的方法，其中可以防止产生Si点蚀现象。 该组合物包括含有羟基离子（OH）的化合物，含有氟离子（F）的化合物和足够量的氧化剂以控制pH 的组合物在约6.5至约8.0的范围内。 该方法包括通过使用等离子体的干蚀刻来干蚀刻氧化物，然后使用灰化工艺灰化蚀刻的氧化物以除去有机材料。 该方法还包括提供有机剥离组合物以除去包括任何残余有机材料，金属聚合物和氧化物型聚合物的残余物。 汽提组合物对各种金属是稳定的，不会引起Si点蚀现象。

    Methods of forming non-volatile memory devices having floating gate electrodes
    9.
    发明授权
    Methods of forming non-volatile memory devices having floating gate electrodes 失效
    形成具有浮动栅电极的非易失性存储器件的方法

    公开(公告)号：US07445997B2

    公开(公告)日：2008-11-04

    申请号：US11103069

    申请日：2005-04-11

    申请人： Won-Jun Lee ,  Tae-Hyun Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Byoung-Moon Yoon ,  Ji-Hong Kim

    发明人： Won-Jun Lee ,  Tae-Hyun Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Byoung-Moon Yoon ,  Ji-Hong Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Methods of forming non-volatile memory devices include the steps of forming a semiconductor substrate having first and second floating gate electrodes thereon and an electrically insulating region extending between the first and second floating gate electrodes. A step is then performed to etch back the electrically insulating region to expose upper corners of the first and second floating gate electrodes. Another etching step is then performed. This etching step includes exposing upper surfaces and the exposed upper corners of the first and second floating gate electrodes to an etchant that rounds the exposed upper corners of the first and second floating gate electrodes. The step of etching back the electrically insulating region includes etching back the electrically insulating region to expose sidewalls of the first and second floating gate electrodes having heights ranging from about 30 Å to about 200 Å. The step of exposing the upper corners of the first and second floating gate electrodes to an etchant is followed by the step of etching back the electrically insulating region to expose entire sidewalls of the first and second floating gate electrodes.

    摘要翻译： 形成非易失性存储器件的方法包括以下步骤：在其上形成具有第一和第二浮栅的半导体衬底和在第一和第二浮栅之间延伸的电绝缘区。 然后执行步骤以回蚀电绝缘区域以暴露第一和第二浮栅电极的上角。 然后执行另一蚀刻步骤。 该蚀刻步骤包括将第一和第二浮栅电极的上表面和暴露的上角露出到蚀刻剂，该蚀刻剂围绕第一和第二浮栅的暴露的上角。 蚀刻回电绝缘区域的步骤包括蚀刻电绝缘区域以暴露第一和第二浮栅电极的侧壁，其高度范围为约至约200。 将第一和第二浮栅的上角暴露于蚀刻剂的步骤之后是蚀刻电绝缘区以暴露第一和第二浮栅的整个侧壁的步骤。

    Methods of forming non-volatile memory devices having floating gate electrodes
    10.
    发明申请
    Methods of forming non-volatile memory devices having floating gate electrodes 失效
    形成具有浮动栅电极的非易失性存储器件的方法

    公开(公告)号：US20050255654A1

    公开(公告)日：2005-11-17

    申请号：US11103069

    申请日：2005-04-11

    申请人： Won-Jun Lee ,  Tae-Hyun Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Byoung-Moon Yoon ,  Ji-Hong Kim

    发明人： Won-Jun Lee ,  Tae-Hyun Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim ,  Byoung-Moon Yoon ,  Ji-Hong Kim

    IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Methods of forming non-volatile memory devices include the steps of forming a semiconductor substrate having first and second floating gate electrodes thereon and an electrically insulating region extending between the first and second floating gate electrodes. A step is then performed to etch back the electrically insulating region to expose upper corners of the first and second floating gate electrodes. Another etching step is then performed. This etching step includes exposing upper surfaces and the exposed upper corners of the first and second floating gate electrodes to an etchant that rounds the exposed upper corners of the first and second floating gate electrodes. The step of etching back the electrically insulating region includes etching back the electrically insulating region to expose sidewalls of the first and second floating gate electrodes having heights ranging from about 30 Å to about 200 Å. The step of exposing the upper corners of the first and second floating gate electrodes to an etchant is followed by the step of etching back the electrically insulating region to expose entire sidewalls of the first and second floating gate electrodes.

    摘要翻译： 形成非易失性存储器件的方法包括以下步骤：在其上形成具有第一和第二浮栅的半导体衬底和在第一和第二浮栅之间延伸的电绝缘区。 然后执行步骤以回蚀电绝缘区域以暴露第一和第二浮栅电极的上角。 然后执行另一蚀刻步骤。 该蚀刻步骤包括将第一和第二浮栅电极的上表面和暴露的上角露出到蚀刻剂，该蚀刻剂围绕第一和第二浮栅的暴露的上角。 蚀刻回电绝缘区域的步骤包括蚀刻电绝缘区域以暴露第一和第二浮栅电极的侧壁，其高度范围为约至约200。 将第一和第二浮栅的上角暴露于蚀刻剂的步骤之后是蚀刻电绝缘区以暴露第一和第二浮栅的整个侧壁的步骤。