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    OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE
    5.
    发明申请
    OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE 有权
    通过掩蔽和反应离子蚀刻（RIE）技术的超耐性

    公开(公告)号：US20140061930A1

    公开(公告)日：2014-03-06

    申请号：US13604660

    申请日：2012-09-06

    申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

    摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.

    摘要翻译： 提供了一种方法，其包括首先根据第一掩模蚀刻衬底。 第一蚀刻在衬底中形成第一深度的第一蚀刻特征。 第一蚀刻还在衬底中形成条条开口。 然后可以用填充材料填充条子开口。 可以通过去除第一掩模的一部分来形成第二掩模。 可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。 第二蚀刻将第一蚀刻特征延伸到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。 然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。

    DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME
    6.
    发明申请
    DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME 有权
    双重对等双向对联方案

    公开(公告)号：US20130328208A1

    公开(公告)日：2013-12-12

    申请号：US13490542

    申请日：2012-06-07

    申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L23/48 ,  H01L21/28

    CPC分类号： H01L21/76897 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

    摘要翻译： 在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。 之后形成第二电介质材料层。 在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。 将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。 通过对第一和第二介电材料层的介电材料的选择性蚀刻来去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制并沿着宽度方向的 第一条金属线。 形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。

    Method of forming borderless contact for transistor
    7.
    发明授权
    Method of forming borderless contact for transistor 失效
    形成晶体管无边界接触的方法

    公开(公告)号：US08232204B1

    公开(公告)日：2012-07-31

    申请号：US13171527

    申请日：2011-06-29

    申请人： David V. Horak ,  Charles W. Koburger, III ,  Steven J. Holmes ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： David V. Horak ,  Charles W. Koburger, III ,  Steven J. Holmes ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76834 ,  H01L21/76897 ,  H01L29/49 ,  H01L29/78

    摘要： Embodiments of the present invention provide a method of forming borderless contact for transistor. The method may include forming a gate of a transistor, on top of a substrate, and spacers adjacent to sidewalls of the gate; forming a sacrificial layer surrounding the gate; causing the sacrificial layer to expand in height to become higher than the gate, the expanded sacrificial layer covering at most a portion of a top surface of the spacers and thereby leaving an opening on top of the gate surrounded by the spacers; filling the opening with a dielectric cap layer; replacing the expanded sacrificial layer with a dielectric layer; and forming a conductive stud contacting source/drain of the transistor, the conductive stud being isolated from the gate by the dielectric cap layer.

    摘要翻译： 本发明的实施例提供一种形成晶体管的无边界接触的方法。 该方法可以包括在衬底的顶部上形成晶体管的栅极和邻近栅极的侧壁的间隔物; 形成围绕所述栅极的牺牲层; 导致牺牲层在高度上膨胀以变得高于栅极，所述扩展的牺牲层覆盖所述间隔物的顶表面的至多一部分，从而在由所述间隔物包围的所述栅极的顶部上留下开口; 用介电盖层填充开口; 用介电层代替扩展的牺牲层; 并且形成与晶体管的导电柱接触的源极/漏极，导电柱通过电介质盖层与栅极隔离。

    Dual damascene dual alignment interconnect scheme
    8.
    发明授权
    Dual damascene dual alignment interconnect scheme 有权
    双镶嵌双对准互连方案

    公开(公告)号：US08803321B2

    公开(公告)日：2014-08-12

    申请号：US13490542

    申请日：2012-06-07

    申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L23/535 ,  H01L21/283

    CPC分类号： H01L21/76897 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

    摘要翻译： 在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。 此后形成第二电介质材料层。 在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。 将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。 通过对第一和第二介电材料层的电介质材料的选择性蚀刻去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制的通孔腔，并沿着宽度方向 第一条金属线。 形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。

    DUAL-METAL SELF-ALIGNED WIRES AND VIAS
    9.
    发明申请
    DUAL-METAL SELF-ALIGNED WIRES AND VIAS 有权
    双金属自对准线和VIAS

    公开(公告)号：US20130207270A1

    公开(公告)日：2013-08-15

    申请号：US13371493

    申请日：2012-02-13

    申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L21/768 ,  H01L23/49

    CPC分类号： H01L23/485 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5283 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.

    摘要翻译： 形成半导体结构的方法，包括在半导体衬底上形成第一导电间隔物; 相对于所述第一导电间隔物形成第二导电间隔物，所述第二导电间隔物中的至少一个与所述第一导电间隔物中的每一个相邻并与之接触以形成组合的导电间隔物; 相对于第一导电间隔物使第二导电间隔物凹陷，使得第一导电间隔物延伸超过第二导电间隔物; 沉积ILD以覆盖除了第一导电间隔物的暴露边缘之外的第一和第二间隔物; 图案化第一导电间隔物的暴露边缘以将预定位置中的第一导电间隔物的边缘凹入以形成相对于ILD的凹部; 并用绝缘材料填充凹槽，以将第一导电间隔物的未加工的边缘作为过孔留下以后的布线特征。

    Overlay-tolerant via mask and reactive ion etch (RIE) technique
    10.
    发明授权
    Overlay-tolerant via mask and reactive ion etch (RIE) technique 有权
    覆盖层通过掩模和反应离子蚀刻（RIE）技术

    公开(公告)号：US09059254B2

    公开(公告)日：2015-06-16

    申请号：US13604660

    申请日：2012-09-06

    申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L21/311

    CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

    摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.

    摘要翻译： 提供了一种方法，其包括首先根据第一掩模蚀刻衬底。 第一蚀刻在衬底中形成第一深度的第一蚀刻特征。 第一蚀刻还在衬底中形成条条开口。 然后可以用填充材料填充条子开口。 可以通过去除第一掩模的一部分来形成第二掩模。 可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。 第二蚀刻将第一蚀刻特征扩展到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。 然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。