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    Positive and negative voltage level shifter circuit
    1.
    发明授权
    Positive and negative voltage level shifter circuit 有权
    正，负电压电平转换电路

    公开(公告)号：US08270234B1

    公开(公告)日：2012-09-18

    申请号：US13113303

    申请日：2011-05-23

    申请人： Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

    发明人： Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1078 ,  G11C7/1084 ,  H03K3/356052 ,  H03K3/356113

    摘要： A level shifter including a level shifter module configured to i) receive an input signal, wherein the input signal varies between a first level and a second level, ii) receive a first voltage supply signal and a second voltage supply signal, and iii) generate a latch control signal based on the input signal and one of the first voltage supply signal and the second voltage supply signal. The level shifter further includes a latch module configured to i) receive the latch control signal, ii) receive the second voltage supply signal and a third voltage supply signal, and iii) generate an output signal based on the latch control signal and one of the second voltage supply signal and the third voltage supply signal.

    摘要翻译： 一种电平移位器，包括电平移位器模块，其配置为i）接收输入信号，其中所述输入信号在第一电平和第二电平之间变化，ii）接收第一电压供应信号和第二电压供应信号，以及iii）产生 基于输入信号和第一电压供给信号和第二电压供给信号中的一个的锁存器控制信号。 电平移位器还包括锁存模块，其被配置为i）接收锁存控制信号，ii）接收第二电压供应信号和第三电压供应信号，以及iii）基于锁存控制信号产生输出信号，并且 第二电压供给信号和第三电压供给信号。

    Non-volatile memory cell and array
    2.
    发明授权
    Non-volatile memory cell and array 有权
    非易失性存储单元和阵列

    公开(公告)号：US08120088B1

    公开(公告)日：2012-02-21

    申请号：US12105988

    申请日：2008-04-18

    申请人： Min She ,  Chih-Hsin Wang

    发明人： Min She ,  Chih-Hsin Wang

    IPC分类号： H01L29/76

    CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： Memory cells and arrays have reduced bit line resistance. An element conductor is disposed on the top of the bit line to reduce the resistance of the bit line while maintaining a shallow bit line junction so that 200 Ohm/square or lower sheet resistances are achieved with the bit line junctions typically 20 nanometers or shallower while the doping levels in the junctions are below about 5×1019 atoms/cm3.

    摘要翻译： 存储单元和阵列降低了位线电阻。 元件导体设置在位线的顶部以减小位线的电阻，同时保持浅位线结，使得通过20位或更浅的位线结实现200欧姆/平方或更小的薄层电阻，同时 结中的掺杂水平低于约5×1019原子/ cm3。

    ELECTRICALLY ALTERABLE NON-VOLATILE MEMORY CELLS AND ARRAYS
    3.
    发明申请
    ELECTRICALLY ALTERABLE NON-VOLATILE MEMORY CELLS AND ARRAYS 失效
    电可更换的非易失性记忆细胞和阵列

    公开(公告)号：US20070253257A1

    公开(公告)日：2007-11-01

    申请号：US11380418

    申请日：2006-04-26

    申请人： Chih-Hsin Wang

    发明人： Chih-Hsin Wang

    IPC分类号： G11C16/04

    CPC分类号： H01L29/7885 ,  G11C16/0416 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324

    摘要： Nonvolatile memory cells and array are provided. The memory cell comprises a body, a source, a drain, and a charge storage region. The body comprises an n-type conductivity and is formed in a well of the n-type conductivity. The source and the drain have p-type conductivity and are formed in the well with a channel of the body defined therebetween. The charge storage region is disposed over and insulated from the channel by a channel insulator. Each cell further comprises a bias setting having a source voltage applied to the source, a well voltage applied to the well, and a drain voltage applied to the drain. A bias configuration for an erase operation of the memory cell is further provided, wherein the source voltage is sufficiently more negative with respect to the well voltage and is sufficiently more positive with respect to the drain voltage to inject hot holes onto the charge storage region. The cells can be arranged in row and column to form memory arrays and memory device.

    摘要翻译： 提供了非易失性存储单元和阵列。 存储单元包括主体，源极，漏极和电荷存储区域。 该主体包括n型导电性并形成在n型导电性的阱中。 源极和漏极具有p型导电性，并且在阱中形成有在其间限定的主体的沟道。 电荷存储区域通过沟道绝缘体设置在通道上并与通道绝缘。 每个单元还包括具有施加到源极的源极电压，施加到阱的阱电压和施加到漏极的漏极电压的偏置设置。 还提供了用于存储单元的擦除操作的偏置配置，其中源极电压相对于阱电压足够多地为负，并且相对于漏极电压而言足够地为正向，以将热空穴注入电荷存储区域。 单元格可以以行和列排列以形成存储器阵列和存储器件。

    P-channel electrically alterable non-volatile memory cell
    4.
    发明授权
    P-channel electrically alterable non-volatile memory cell 有权
    P沟道电可变非易失性存储单元

    公开(公告)号：US07180125B2

    公开(公告)日：2007-02-20

    申请号：US10962288

    申请日：2004-10-08

    申请人： Chih-Hsin Wang

    发明人： Chih-Hsin Wang

    IPC分类号： H01L29/788

    CPC分类号： G11C16/0416 ,  G11C16/14 ,  H01L29/42332 ,  H01L29/7885 ,  H01L29/792

    摘要： A nonvolatile memory cell is provided. The memory cell comprises a storage transistor and an injector in a semiconductor substrate of a p-type conductivity. The injector comprises a first region of the p-type conductivity and a second region of an n-type conductivity. The storage transistor comprises a source, a drain, a channel, a charge storage region, and a control gate. The source and the drain have the p-type conductivity and are formed in a well of the n-type conductivity in the substrate with the channel of the well defined therebetween. The charge storage region is disposed over and insulated from the channel by a first insulator. The control gate is disposed over and insulated from the charge storage region by a second insulator. Further provided are methods operating the memory cell, including means for injecting electrons from the channel through the first insulator onto the charge storage region and means for injecting holes from the injector through the well through the channel through the first insulator onto the charge storage region.

    摘要翻译： 提供非易失性存储单元。 存储单元包括p型导电性的半导体衬底中的存储晶体管和注入器。 注射器包括p型导电性的第一区域和n型导电性的第二区域。 存储晶体管包括源极，漏极，沟道，电荷存储区域和控制栅极。 源极和漏极具有p型导电性，并且形成在衬底中的n型导电性的阱中，阱之间的沟道被限定。 电荷存储区域通过第一绝缘体设置在沟道之上并与沟道绝缘。 控制栅极通过第二绝缘体设置在电荷存储区域之上并与电荷存储区域绝缘。 还提供了操作存储单元的方法，包括用于将电子从通道中通过第一绝缘体注入到电荷存储区上的装置，以及用于将来自注射器的孔穿过阱通过穿过第一绝缘体的沟道注入到电荷存储区上的装置。

    METHODS FOR OPERATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    METHODS FOR OPERATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE 失效
    用于操作半导体器件和半导体存储器件的方法

    公开(公告)号：US20070008778A1

    公开(公告)日：2007-01-11

    申请号：US11464404

    申请日：2006-09-25

    申请人： Chih-Hsin Wang

    发明人： Chih-Hsin Wang

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3418 ,  G11C16/3427

    摘要： Methods and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for semiconductor device and nonvolatile memory device. The device comprises a strain source, an injection filter, a first conductive region, a second conductive region, and a third conductive region. The strain source permits piezo-effect in ballistic charges transport to enable the piezo-ballistic-charges injection mechanism in device operations. The injection filter permits transporting of charge carriers of one polarity type from the first conductive region, through the filter, and through the second conductive region to the third conductive region while blocking the transport of charge carriers of an opposite polarity from the second conductive region to the first conductive region. The present invention further provides an energy band engineering method permitting the devices be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.

    摘要翻译： 为半导体器件和非易失性存储器件提供使用压电弹药注入机构的电荷注入的方法和装置。 该装置包括应变源，注射过滤器，第一导电区域，第二导电区域和第三导电区域。 应变源允许在弹道电荷输送中的压电效应，使得能够在器件操作中实现压电弹药注入机制。 注入过滤器允许将一种极性类型的电荷载体从第一导电区域通过滤波器传输，并且通过第二导电区域传输到第三导电区域，同时阻止相反极性的电荷载体从第二导电区域传输到 第一导电区域。 本发明进一步提供一种能量带工程方法，其允许在不受到电介质击穿，不受冲击电离和不期望的RC影响的干扰的情况下操作装置。

    Low power electrically alterable nonvolatile memory cells and arrays
    6.
    发明申请
    Low power electrically alterable nonvolatile memory cells and arrays 有权
    低功率电气可变非易失性存储器单元和阵列

    公开(公告)号：US20060289924A1

    公开(公告)日：2006-12-28

    申请号：US11234646

    申请日：2005-09-23

    申请人： Chih-Hsin Wang

    发明人： Chih-Hsin Wang

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/26586 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/47 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    摘要： Nonvolatile memory cells having a conductor-filter system, a conductor-insulator system, and a charge-injection system are provided. The conductor-filter system provides band-pass filtering function, charge-filtering function, and mass-filtering function to charge-carriers flows. The conductor-insulator system provides Image-Force barrier lowering effect to collect charge-carriers. The charge-injection system includes the conductor-filter system and the conductor-insulator system, wherein the filter of the conductor-filter system contacts the conductor of the conductor-insulator system. Apparatus on cell architecture are provided for the nonvolatile memory cells. Additionally, apparatus on array architectures are provided for constructing the nonvolatile memory cells in memory array. Method on manufacturing such memory cells and array architectures are provided.

    摘要翻译： 提供具有导体滤波器系统，导体 - 绝缘体系统和电荷注入系统的非易失性存储单元。 导体滤波器系统为电荷载流子提供带通滤波功能，电荷滤波功能和质量滤波功能。 导体 - 绝缘体系统提供图像强制屏障降低效应以收集电荷载体。 电荷注入系统包括导体 - 滤波器系统和导体 - 绝缘体系统，其中导体 - 滤波器系统的滤波器接触导体 - 绝缘体系统的导体。 为非易失性存储单元提供了单元结构的装置。 此外，提供了阵列架构上的装置用于构建存储器阵列中的非易失性存储单元。 提供了制造这种存储单元和阵列架构的方法。

    Method and apparatus for nonvolatile memory
    7.
    发明授权
    Method and apparatus for nonvolatile memory 有权
    非易失性存储器的方法和装置

    公开(公告)号：US07115942B2

    公开(公告)日：2006-10-03

    申请号：US11007907

    申请日：2004-12-08

    申请人： Chih-Hsin Wang

    发明人： Chih-Hsin Wang

    IPC分类号： H01L29/76 ,  G11C16/04

    CPC分类号： H01L27/11568 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    摘要： Method and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for nonvolatile memory device. The device has a strain source, an injection filter, a tunneling gate, a ballistic gate, a charge storage region, a source, and a drain with a channel defined between the source and drain. The strain source permits piezo-effect in ballistic charges transport to enable the piezo-ballistic-charges injection mechanism. The injection filter permits transporting of charge carriers of one polarity type from the tunneling gate through the blocking material and the ballistic gate to the charge storage region while blocking the transport of charge carriers of an opposite polarity from the ballistic gate to the tunneling gate. The present invention further provides an energy band engineering method permitting the memory device be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.

    摘要翻译： 为非易失性存储器件提供使用压电弹药注入机构的电荷注入的方法和装置。 该装置具有在源极和漏极之间限定的通道的应变源，注入滤波器，隧道栅极，弹道栅极，电荷存储区域，源极和漏极。 应变源允许弹道电荷输送中的压电效应，以实现压电弹药注入机制。 注入过滤器允许将一种极性类型的电荷载体从隧道栅极通过阻挡材料和防弹门传送到电荷存储区域，同时阻止相反极性的电荷载体从弹道栅极传输到隧道栅极。 本发明进一步提供一种能量带工程方法，其允许存储器件在不遭受电介质击穿的影响，不受冲击电离以及不期望的RC影响的情况下操作。

    Method and apparatus for nonvolatile memory
    9.
    发明申请
    Method and apparatus for nonvolatile memory 有权

    公开(公告)号：US20060017091A1

    公开(公告)日：2006-01-26

    申请号：US11007907

    申请日：2004-12-08

    申请人： Chih-Hsin Wang

    发明人： Chih-Hsin Wang

    IPC分类号： H01L29/94

    CPC分类号： H01L27/11568 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    摘要： Method and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for nonvolatile memory device. The device has a strain source, an injection filter, a tunneling gate, a ballistic gate, a charge storage region, a source, and a drain with a channel defined between the source and drain. The strain source permits piezo-effect in ballistic charges transport to enable the piezo-ballistic-charges injection mechanism. The injection filter permits transporting of charge carriers of one polarity type from the tunneling gate through the blocking material and the ballistic gate to the charge storage region while blocking the transport of charge carriers of an opposite polarity from the ballistic gate to the tunneling gate. The present invention further provides an energy band engineering method permitting the memory device be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.