公开(公告)号：US08928065B2

公开(公告)日：2015-01-06

申请号：US12909033

申请日：2010-10-21

申请人： Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

发明人： Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

IPC分类号： H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover at least a portion of the termination structure oxide layer.

摘要翻译： 功率晶体管的端接结构包括具有有源区和端接区的半导体衬底。 衬底具有第一类导电性。 终端沟槽位于终端区域中并且从有源区域的边界延伸到半导体衬底的边缘的一定距离内。 掺杂区域具有设置在终端沟槽下方的衬底中的第二类型的导电体。 在与边界相邻的侧壁上形成MOS栅极。 掺杂区域从与边界间隔开的部分MOS栅极的下方延伸到终端沟槽的远侧侧壁。 端接结构氧化物层形成在终端沟槽上并且覆盖MOS栅极的一部分并朝向衬底的边缘延伸。 第一导电层形成在半导体衬底的背面上。 第二导电层形成在有源区顶部，MOS栅极的暴露部分的顶部，并延伸以覆盖端接结构氧化物层的至少一部分。

公开(公告)号：US08816468B2

公开(公告)日：2014-08-26

申请号：US13222249

申请日：2011-08-31

申请人： Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

发明人： Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

IPC分类号： H01L29/872

CPC分类号： H01L29/66143 ,  H01L21/22 ,  H01L21/265 ,  H01L29/0619 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.

摘要翻译： 半导体整流器包括具有第一类导电性的半导体衬底。 形成在基板上的第一层具有第一类导电性，并且比衬底更轻掺杂。 在基板上形成具有第二导电类型的第二层，并且金属层设置在第二层上。 第二层被轻掺杂，使得在金属层和第二层之间形成肖特基接触。 第一电极形成在金属层的上方，第二电极形成在基板的背面。

公开(公告)号：US08853770B2

公开(公告)日：2014-10-07

申请号：US12724771

申请日：2010-03-16

申请人： Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

发明人： Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

IPC分类号： H01L29/76 ,  H01L29/40 ,  H01L29/06 ,  H01L29/78 ,  H01L29/872

CPC分类号： H01L29/407 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/404 ,  H01L29/66143 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： A termination structure is provided for a power transistor. The termination structure includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A doped region having a second type of conductivity is disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward the edge of the semiconductor substrate. A termination structure oxide layer is formed on the termination trench covering a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate and a second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover a portion of the termination structure oxide layer.

摘要翻译： 为功率晶体管提供终端结构。 端接结构包括具有有源区和端接区的半导体衬底。 衬底具有第一类导电性。 终端沟槽位于终端区域中并且从有源区域的边界朝向半导体衬底的边缘延伸。 具有第二类型的导电性的掺杂区域设置在终端沟槽下方的衬底中。 在与边界相邻的侧壁上形成MOS栅极。 掺杂区域从与栅极间隔开的部分MOS栅极向半导体衬底的边缘延伸。 端接结构氧化物层形成在覆盖MOS栅极的一部分并朝向衬底边缘延伸的端接沟槽上。 第一导电层形成在半导体衬底的背侧表面上，并且第二导电层形成在有源区顶部，MOS栅极的暴露部分之上，并延伸以覆盖端接结构氧化物层的一部分。

公开(公告)号：US20130168765A1

公开(公告)日：2013-07-04

申请号：US13343435

申请日：2012-01-04

申请人： Yih-Yin Lin ,  Pai-Li Lin ,  Chih-Wei Hsu

发明人： Yih-Yin Lin ,  Pai-Li Lin ,  Chih-Wei Hsu

IPC分类号： H01L27/06 ,  H01L21/28

CPC分类号： H01L29/8725 ,  H01L29/0661 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

摘要： A termination structure is provided for a semiconductor device. The termination structure includes a semiconductor substrate having an active region and a termination region. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A MOS gate is formed on a sidewall of the termination trench adjacent the boundary. At least one guard ring trench is formed in the termination region on a side of the termination trench remote from the active region. A termination structure oxide layer is formed on the termination trench and the guard ring trench. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region and the termination region.

摘要翻译： 为半导体器件提供端接结构。 端接结构包括具有有源区和端接区的半导体衬底。 终端沟槽位于终端区域中并且从有源区域的边界朝向半导体衬底的边缘延伸。 在靠近边界的终端沟槽的侧壁上形成MOS栅极。 在远离有源区域的终端沟槽的一侧的终端区域中形成至少一个保护环沟槽。 端接结构氧化层形成在端接沟槽和保护环沟槽上。 第一导电层形成在半导体衬底的背面上。 第二导电层形成在有源区和端接区之上。

公开(公告)号：US06291316B1

公开(公告)日：2001-09-18

申请号：US09233706

申请日：1999-01-19

申请人： Christopher Michael Knowles ,  Yih-Yin Lin ,  Tung-Chieh Lin ,  William John Nelson ,  Hung-Ping Tsai ,  Richard Sean O'Rourke

发明人： Christopher Michael Knowles ,  Yih-Yin Lin ,  Tung-Chieh Lin ,  William John Nelson ,  Hung-Ping Tsai ,  Richard Sean O'Rourke

IPC分类号： H01L2146

CPC分类号： H01L23/3178 ,  H01L21/76224 ,  H01L2924/0002 ,  Y10S438/958 ,  H01L2924/00

摘要： A wafer-level process for fabricating a plurality of passivated semiconductor devices comprising the steps of providing a semiconductor wafer on that at least one p-n junction is formed, Cutting a plurality of grooves in said wafer to expose said at least one p-n junction, wherein each of said grooves extends partly through the wafer and has a depth that is enough to expose said at least one p-n junction, applying a passivating material into said grooves and curing the material. The grooves can be formed by using a disc saw having a blade, by performing a sandblasting operation within a controlled operation time, or by performing a photolithographically chemical etching process. The passivating material is either screen-printed or pin-dispensed into the grooves. A dicing operation can be subsequently proceeded to divide the wafer into individual chips for subsequent fabrication into completed semiconductor devices.

摘要翻译： 一种用于制造多个钝化半导体器件的晶片级工艺，包括以下步骤：在该至少一个pn结上提供半导体晶片;在所述晶片中切割多个凹槽以暴露所述至少一个pn结，其中每个 所述凹槽部分地延伸穿过晶片并且具有足以露出所述至少一个pn结的深度，将钝化材料施加到所述凹槽中并固化材料。 可以通过使用具有叶片的盘锯，通过在受控的操作时间内进行喷砂操作，或通过进行光刻化学蚀刻工艺来形成凹槽。 钝化材料被丝网印刷或销钉分配到凹槽中。 随后可以进行切割操作以将晶片分成单个芯片，以便随后制造成完整的半导体器件。