公开(公告)号：US08547139B2

公开(公告)日：2013-10-01

申请号：US13421159

申请日：2012-03-15

申请人： Chikahiro Hori ,  Akira Takiba

发明人： Chikahiro Hori ,  Akira Takiba

IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03K19/20 ,  H03B1/00 ,  H03L5/00

CPC分类号： H03K3/355 ,  H03K3/35613 ,  H03K19/018528

摘要： A CMOS logic integrated circuit includes a level shifter and a CMOS logic circuit. The level shifter converts a signal of a first logic level to a signal of a second logic level. The signal of the first logic level changes between a first low potential and a first high potential higher than the first low potential. The signal of the second logic level changes between the first low potential and a second high potential higher than the first high potential. The CMOS logic circuit includes a first N-channel type MOSFET and a second N-channel type MOSFET. The second N-channel type MOSFET is connected in series with the first N-channel type MOSFET. A first signal of the first logic level is input into a gate of the first N-channel type MOSFET. A second signal of the second logic level has an inversion relationship with the first signal.

摘要翻译： CMOS逻辑集成电路包括电平转换器和CMOS逻辑电路。 电平移位器将第一逻辑电平的信号转换为第二逻辑电平的信号。 第一逻辑电平的信号在第一低电位和高于第一低电位的第一高电位之间变化。 第二逻辑电平的信号在第一低电位和高于第一高电位的第二高电位之间变化。 CMOS逻辑电路包括第一N沟道型MOSFET和第二N沟道型MOSFET。 第二N沟道型MOSFET与第一N沟道型MOSFET串联连接。 第一逻辑电平的第一信号被输入到第一N沟道型MOSFET的栅极中。 第二逻辑电平的第二信号与第一信号具有反相关系。

公开(公告)号：US20070001771A1

公开(公告)日：2007-01-04

申请号：US11476554

申请日：2006-06-29

申请人： Chikahiro Hori ,  Akira Takiba ,  Masanori Kinugasa

发明人： Chikahiro Hori ,  Akira Takiba ,  Masanori Kinugasa

IPC分类号： H03K3/03

CPC分类号： H03K3/0315 ,  H03K5/00006 ,  H03K5/133

摘要： An oscillation circuit comprises a ring oscillator configured to have at least an odd number of stages of inverters, and a frequency multiplier section configured to output as a multiplied output, an exclusive OR of signals taken out from the inverters at least at two stages of the ring oscillator.

摘要翻译： 振荡电路包括：环形振荡器，被配置为具有至少奇数级的反相器;以及倍增器部分，被配置为输出作为相乘的输出，至少在所述反相器的两个阶段从所述反相器中取出的信号的异或 环形振荡器。

公开(公告)号：US20130015883A1

公开(公告)日：2013-01-17

申请号：US13421159

申请日：2012-03-15

申请人： Chikahiro HORI ,  Akira Takiba

发明人： Chikahiro HORI ,  Akira Takiba

IPC分类号： H03K19/0175

CPC分类号： H03K3/355 ,  H03K3/35613 ,  H03K19/018528

摘要： A CMOS logic integrated circuit includes a level shifter and a CMOS logic circuit. The level shifter converts a signal of a first logic level to a signal of a second logic level. The signal of the first logic level changes between a first low potential and a first high potential higher than the first low potential. The signal of the second logic level changes between the first low potential and a second high potential higher than the first high potential. The CMOS logic circuit includes a first N-channel type MOSFET and a second N-channel type MOSFET. The second N-channel type MOSFET is connected in series with the first N-channel type MOSFET. A first signal of the first logic level is input into a gate of the first N-channel type MOSFET. A second signal of the second logic level has an inversion relationship with the first signal.

摘要翻译： CMOS逻辑集成电路包括电平转换器和CMOS逻辑电路。 电平移位器将第一逻辑电平的信号转换为第二逻辑电平的信号。 第一逻辑电平的信号在第一低电位和高于第一低电位的第一高电位之间变化。 第二逻辑电平的信号在第一低电位和高于第一高电位的第二高电位之间变化。 CMOS逻辑电路包括第一N沟道型MOSFET和第二N沟道型MOSFET。 第二N沟道型MOSFET与第一N沟道型MOSFET串联连接。 第一逻辑电平的第一信号被输入到第一N沟道型MOSFET的栅极中。 第二逻辑电平的第二信号与第一信号具有反相关系。

公开(公告)号：US07358773B2

公开(公告)日：2008-04-15

申请号：US11689826

申请日：2007-03-22

申请人： Akira Takiba

发明人： Akira Takiba

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521

摘要： The signal level conversion circuit has a first terminal for a signal of a low power voltage; a second terminal for a signal of a high power voltage higher than the low power voltage; a level shifter which is disposed in a signal path from the first terminal to the second terminal to convert the low power voltage signal into the high power voltage signal; and a first input buffer including a first inverter of P1 and N1 whose gates are connected to the first terminal, and a one-way device between a voltage supply of the low power voltage and a source of P1. The level shifter includes second and third inverters which are interposed between an output of the first input buffer and the second terminal and which use the high power voltage and which are connected in series, an output of the first input buffer is supplied to an input of the second inverter and an output of the third inverter, and a circuit threshold value of the second inverter using the high power voltage is set to be lower than a voltage obtained by subtracting a voltage drop consumed by the one-way device from the low power voltage. A first logic circuit for calculating the signal of the low or high power voltage is disposed in a certain portion of the signal path, and a circuit threshold value of the first logic circuit is set to be lower than a voltage obtained by subtracting a voltage drop consumed by the one-way device from the low power voltage.

摘要翻译： 信号电平转换电路具有用于低功率电压信号的第一端子; 用于高于低功率电压的高功率电压的信号的第二端子; 电平移位器，设置在从第一端子到第二端子的信号路径中，以将低功率电压信号转换成高功率电压信号; 以及第一输入缓冲器，其包括其栅极连接到第一端子的P 1和N 1的第一反相器，以及在低功率电压的电压源和P 1源之间的单向器件。 电平移位器包括第二和第三反相器，其被插入在第一输入缓冲器的输出端和第二端子之间并且使用高功率电压并串联连接的第二和第三反相器，第一输入缓冲器的输出被提供给 第二反相器和第三反相器的输出以及使用高功率电压的第二反相器的电路阈值被设置为低于通过从低功率减去单向器件消耗的电压降而获得的电压 电压。 用于计算低电压或高功率电压的信号的第一逻辑电路被布置在信号路径的某一部分中，并且第一逻辑电路的电路阈值被设置为低于通过减去电压降 由单向设备从低功率电压消耗。

公开(公告)号：US20120068755A1

公开(公告)日：2012-03-22

申请号：US13052324

申请日：2011-03-21

申请人： Mitsuo Yamamoto ,  Akira Takiba

发明人： Mitsuo Yamamoto ,  Akira Takiba

IPC分类号： H03L5/00

CPC分类号： H03K3/356113

摘要： According to one embodiment, a level shifter includes a high-side switch and a low-side switch. The high-side switch is connected between a high-potential power supply and a connection point and turned on in accordance with an input signal. The low-side switch is connected between the connection point and a low-potential power supply and turned on in accordance with an input signal. A ratio between ON resistance of the high-side switch and ON resistance of the low-side switch is set in accordance with a signal difference between an output signal and the input signal. The output signal is outputted to the connection point.

摘要翻译： 根据一个实施例，电平移位器包括高侧开关和低侧开关。 高侧开关连接在高电位电源和连接点之间，并根据输入信号接通。 低侧开关连接在连接点和低电位电源之间，并根据输入信号接通。 根据输出信号和输入信号之间的信号差，设定高侧开关的导通电阻与低侧开关的导通电阻之间的比率。 输出信号输出到连接点。

公开(公告)号：US20080028121A1

公开(公告)日：2008-01-31

申请号：US11778275

申请日：2007-07-16

申请人： Akira Takiba ,  Masaru Mizuta

发明人： Akira Takiba ,  Masaru Mizuta

IPC分类号： G06F13/36

CPC分类号： G06F13/4072

摘要： A bus switch with level shifting may include a first terminal configured to receive and output a first power supply voltage higher than a reference voltage, a second terminal configured to receive and output a second power supply voltage higher than the first power supply voltage, an output control terminal to which a control signal for controlling a switching between an output permitted state and an output prohibited state is inputted, a first switching element provided between the first terminal and the second terminal and having a gate, a gate control circuit to which signals are inputted from the output control terminal and the second terminal, which supplies gate voltage to the gate of the first switching element, and which controls the first switching element to be conducting or to be non-conducting, and a second switching device provided between a power source of the second power supply voltage and the second terminal, and configured to switch between conducting and non-conducting in accordance with the electric potential of the second terminal

摘要翻译： 具有电平移位的总线开关可以包括被配置为接收和输出高于参考电压的第一电源电压的第一端子，被配置为接收和输出高于第一电源电压的第二电源电压的第二端子， 输入用于控制输出允许状态和输出禁止状态之间的切换的控制信号的控制端子，设置在第一端子和第二端子之间并具有栅极的第一开关元件，栅极控制电路，信号为 从输出控制端子和第二端子输入，该第二端子将栅极电压提供给第一开关元件的栅极，并且控制第一开关元件导通或不导通;以及第二开关器件，其设置在功率 第二电源电压源和第二端子，并被配置为在导通和非导通之间切换 根据第二终端的电位

公开(公告)号：US20050219924A1

公开(公告)日：2005-10-06

申请号：US11143994

申请日：2005-06-03

申请人： Akira Takiba ,  Toru Fujii ,  Tetsuyo Shigehiro

发明人： Akira Takiba ,  Toru Fujii ,  Tetsuyo Shigehiro

IPC分类号： H03K19/0185 ,  G11C7/00

CPC分类号： H03K19/018507

摘要： A signal-level converter is provided between a first terminal and a second terminal. The first terminal is connected to a first logic circuit operating at a first supply voltage higher than a given reference voltage. The second terminal is connected to a second logic circuit operating at a second supply voltage higher than the first supply voltage. The signal-level converter has a switching transistor that forms a current passage between the first and the second terminals in response to a control signal supplied to a gate of the switching transistor and a bus-hold circuitry, provided between the switching transistor and either the first or the second terminal as the output terminal, the other being the input terminal, and configured to convert a voltage level of a signal transferred via the switching transistor into another voltage level at the output terminal. The bus-hold circuitry may have two bus-hold circuits between the input and the output terminals, for two-way signal transfer. The bus-hold circuitry may have one bus-hold circuit between the switching transistor and the output terminal, for one-way signal transfer. These circuit arrangements offer reduced chip size and simplified control operations for accurate output-terminal voltages. Moreover, the arrangements omit one direction-switching terminal in two-way signal transfer.

摘要翻译： 信号电平转换器设置在第一端子和第二端子之间。 第一端子连接到以高于给定参考电压的第一电源电压工作的第一逻辑电路。 第二端子连接到以高于第一电源电压的第二电源电压工作的第二逻辑电路。 信号电平转换器具有开关晶体管，其响应于提供给开关晶体管的栅极的控制信号和设置在开关晶体管和总线保持电路之间的总线保持电路，在第一和第二端子之间形成电流通路 第一端子或第二端子作为输出端子，另一端为输入端子，并且被配置为将经由开关晶体管传送的信号的电压电平转换为输出端子处的另一电压电平。 总线保持电路可以在输入端和输出端之间具有两个总线保持电路，用于双向信号传输。 总线保持电路可以在开关晶体管和输出端之间具有一个总线保持电路，用于单向信号传输。 这些电路安排可以降低芯片尺寸，并简化控制操作，以获得精确的输出端电压。 此外，该布置省略了双向信号传输中的一个方向切换终端。

公开(公告)号：US4988894A

公开(公告)日：1991-01-29

申请号：US365739

申请日：1989-06-14

申请人： Akira Takiba ,  Hiroyoshi Murata ,  Yasoji Suzuki ,  Isao Abe

发明人： Akira Takiba ,  Hiroyoshi Murata ,  Yasoji Suzuki ,  Isao Abe

IPC分类号： H03K17/10 ,  H03K17/693

CPC分类号： H03K17/102 ,  H03K17/693

摘要： A power supply switching circuit includes first to third MOS transistors (P1, P2 and P3) connected in series between a high-potential source and a standard-potential source. The circuit performs a switching operation using a standard-potential and at least one potential which is different from the standard-poential, and outputs plural power supply potentials. The third MOS transistor (P3) is inserted between the first and second MOS transistors (P1 and P2). The back gate of the third transistor (P3) is connected to an output terminal (OUT1) formed between the second transistor (P2) and the third transistor (P3) and prevents the formation of a current path via turned-off transistor (P1) due to the action of a parasitic diode in the first and second transistors caused by potential fluctuations.

公开(公告)号：US06924694B2

公开(公告)日：2005-08-02

申请号：US10647290

申请日：2003-08-26

申请人： Masanori Kinugasa ,  Akira Takiba

发明人： Masanori Kinugasa ,  Akira Takiba

IPC分类号： H01L21/822 ,  H01L27/04 ,  H03K17/60 ,  H03K17/687 ,  H03K19/0175 ,  H01L25/10

CPC分类号： H03K17/6872 ,  H03K2217/0018

摘要： A switch circuit formed on a semiconductor substrate, comprising: a first terminal to which a signal of transmission object is inputted; a second terminal from which a signal of transmission object is outputted; a first transistor formed in a first semiconductor region in said semiconductor substrate, which has one of a source and a drain terminals connected to said first terminal and another thereof connected to said second terminal; a control circuit which controls a gate voltage of said first transistor; and a first rectifying element which has an anode terminal connected to said first terminal, a cathode terminal connected to a power supply terminal of said control circuit, said first rectifying element being formed in a second semiconductor region in said semiconductor substrate separate from said first semiconductor region.

摘要翻译： 一种形成在半导体衬底上的开关电路，包括：输入发送对象的信号的第一端子; 输出发送对象的信号的第二终端; 形成在所述半导体衬底中的第一半导体区域中的第一晶体管，其具有连接到所述第一端子的源极和漏极端子中的一个，并且另一个连接到所述第二端子; 控制所述第一晶体管的栅极电压的控制电路; 以及第一整流元件，其具有连接到所述第一端子的阳极端子，连接到所述控制电路的电源端子的阴极端子，所述第一整流元件形成在所述半导体衬底中的与所述第一半导体分离的第二半导体区域中 地区。

公开(公告)号：US20050156630A1

公开(公告)日：2005-07-21

申请号：US11008305

申请日：2004-12-10

申请人： Akira Takiba

发明人： Akira Takiba

IPC分类号： H03K19/0175 ,  H03K19/0185

CPC分类号： H03K19/018521

摘要： The signal level conversion circuit has a first terminal for a signal of a low power voltage; a second terminal for a signal of a high power voltage higher than the low power voltage; a level shifter which is disposed in a signal path from the first terminal to the second terminal to convert the low power voltage signal into the high power voltage signal; and a first input buffer including a first inverter of P1 and N1 whose gates are connected to the first terminal, and a one-way device between a voltage supply of the low power voltage and a source of P1. The level shifter includes second and third inverters which are interposed between an output of the first input buffer and the second terminal and which use the high power voltage and which are connected in series, an output of the first input buffer is supplied to an input of the second inverter and an output of the third inverter, and a circuit threshold value of the second inverter using the high power voltage is set to be lower than a voltage obtained by subtracting a voltage drop consumed by the one-way device from the low power voltage. A first logic circuit for calculating the signal of the low or high power voltage is disposed in a certain portion of the signal path, and a circuit threshold value of the first logic circuit is set to be lower than a voltage obtained by subtracting a voltage drop consumed by the one-way device from the low power voltage.

摘要翻译： 信号电平转换电路具有用于低功率电压信号的第一端子; 用于高于低功率电压的高功率电压的信号的第二端子; 电平移位器，设置在从第一端子到第二端子的信号路径中，以将低功率电压信号转换成高功率电压信号; 以及第一输入缓冲器，其包括其栅极连接到第一端子的P1和N​​1的第一反相器，以及在低功率电压的电压源和P1的源极之间的单向器件。 电平移位器包括第二和第三反相器，其被插入在第一输入缓冲器的输出端和第二端子之间并且使用高功率电压并串联连接的第二和第三反相器，第一输入缓冲器的输出被提供给 第二反相器和第三反相器的输出以及使用高功率电压的第二反相器的电路阈值被设置为低于通过从低功率减去单向器件消耗的电压降而获得的电压 电压。 用于计算低电压或高功率电压的信号的第一逻辑电路被布置在信号路径的某一部分中，并且第一逻辑电路的电路阈值被设置为低于通过减去电压降 由单向设备从低功率电压消耗。