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    Semiconductor process
    4.
    发明授权
    Semiconductor process 有权
    半导体工艺

    公开(公告)号：US08674433B2

    公开(公告)日：2014-03-18

    申请号：US13216259

    申请日：2011-08-24

    申请人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66795 ,  H01L29/66628

    摘要： A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.

    摘要翻译： 半导体工艺包括以下步骤。 提供基板。 在基板上形成至少一个鳍状结构。 在基板上形成氧化层，而不形成鳍状结构。 形成栅极以覆盖氧化物层的一部分和鳍状结构的一部分。 进行蚀刻处理以蚀刻栅极旁边的鳍状结构的一部分，因此在鳍状结构中至少形成凹部。 执行外延工艺以在凹部中形成外延层，其中外延层具有六边形轮廓结构。

    Multi-gate field-effect transistor and process thereof
    6.
    发明授权
    Multi-gate field-effect transistor and process thereof 有权
    多栅极场效应晶体管及其工艺

    公开(公告)号：US08796695B2

    公开(公告)日：2014-08-05

    申请号：US13530127

    申请日：2012-06-22

    申请人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    IPC分类号： H01L29/772

    CPC分类号： H01L29/66795 ,  H01L29/1054 ,  H01L29/66484 ,  H01L29/785

    摘要： A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

    摘要翻译： 多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。 鳍状结构位于基板上。 栅极结构设置在鳍状结构和衬底的一部分上。 外延结构位于栅极结构旁边的鳍状结构上。 梯度盖层位于每个外延结构上。 梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从下到上减小的梯度分布。 此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

    MULTI-GATE FIELD-EFFECT TRANSISTOR AND PROCESS THEREOF
    7.
    发明申请
    MULTI-GATE FIELD-EFFECT TRANSISTOR AND PROCESS THEREOF 有权
    多栅极场效应晶体管及其工艺

    公开(公告)号：US20130341638A1

    公开(公告)日：2013-12-26

    申请号：US13530127

    申请日：2012-06-22

    申请人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    IPC分类号： H01L29/772 ,  H01L21/20 ,  H01L29/161

    CPC分类号： H01L29/66795 ,  H01L29/1054 ,  H01L29/66484 ,  H01L29/785

    摘要： A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

    摘要翻译： 多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。 鳍状结构位于基板上。 栅极结构设置在鳍状结构和衬底的一部分上。 外延结构位于栅极结构旁边的鳍状结构上。 梯度盖层位于每个外延结构上。 梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从下到上减小的梯度分布。 此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

    SEMICONDUCTOR PROCESS
    8.
    发明申请
    SEMICONDUCTOR PROCESS 有权
    半导体工艺

    公开(公告)号：US20130052778A1

    公开(公告)日：2013-02-28

    申请号：US13216259

    申请日：2011-08-24

    申请人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66795 ,  H01L29/66628

    摘要： A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.

    摘要翻译： 半导体工艺包括以下步骤。 提供基板。 在基板上形成至少一个鳍状结构。 在基板上形成氧化层，而不形成鳍状结构。 形成栅极以覆盖氧化物层的一部分和鳍状结构的一部分。 进行蚀刻处理以蚀刻栅极旁边的鳍状结构的一部分，因此在鳍状结构中至少形成凹部。 执行外延工艺以在凹部中形成外延层，其中外延层具有六边形轮廓结构。

    Method for fabricating first and second epitaxial cap layers
    9.
    发明授权
    Method for fabricating first and second epitaxial cap layers 有权
    用于制造第一和第二外延盖层的方法

    公开(公告)号：US08647953B2

    公开(公告)日：2014-02-11

    申请号：US13299044

    申请日：2011-11-17

    申请人： Chin-I Liao ,  I-Ming Lai ,  Chin-Cheng Chien

    发明人： Chin-I Liao ,  I-Ming Lai ,  Chin-Cheng Chien

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823814 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    摘要： A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers. Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.

    摘要翻译： 描述了一种用于制造金属氧化物半导体（MOS）器件的方法，包括以下步骤。 在基板上形成两个凹部。 进行第一外延生长工艺，以在每个凹部中形成第一半导体化合物层。 在外延温度低于700℃的条件下进行第二外延生长工艺，以便在每个第一半导体化合物层上形成覆盖层。 每个盖层包括从基板的表面突出的第二半导体化合物层。 第一和第二半导体化合物层由第一IV族元素和第二种IV族元素组成，其中第二族IV元素是非硅元素。 第二半导体化合物层中的第二IV族元素的含量小于第一半导体化合物层中的含量。

    MOS DEVICE AND METHOD FOR FABRICATING THE SAME
    10.
    发明申请
    MOS DEVICE AND METHOD FOR FABRICATING THE SAME 有权
    MOS器件及其制造方法

    公开(公告)号：US20130126949A1

    公开(公告)日：2013-05-23

    申请号：US13299044

    申请日：2011-11-17

    申请人： Chin-I Liao ,  I-Ming Lai ,  Chin-Cheng Chien

    发明人： Chin-I Liao ,  I-Ming Lai ,  Chin-Cheng Chien

    IPC分类号： H01L29/78 ,  H01L21/20

    CPC分类号： H01L21/823814 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    摘要： A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers. Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.

    摘要翻译： 描述了一种用于制造金属氧化物半导体（MOS）器件的方法，包括以下步骤。 在基板上形成两个凹部。 进行第一外延生长工艺，以便在每个凹部中形成第一半导体化合物层。 在外延温度低于700℃的条件下进行第二外延生长工艺，以便在每个第一半导体化合物层上形成覆盖层。 每个盖层包括从基板的表面突出的第二半导体化合物层。 第一和第二半导体化合物层由第一IV族元素和第二种IV族元素组成，其中第二族IV元素是非硅元素。 第二半导体化合物层中的第二IV族元素的含量小于第一半导体化合物层中的含量。