公开(公告)号：US09006801B2

公开(公告)日：2015-04-14

申请号：US13013081

申请日：2011-01-25

申请人： Christian Lavoie ,  Zhengwen Li ,  Ahmet S. Ozcan ,  Filippos Papadatos ,  Chengwen Pei ,  Jian Yu

发明人： Christian Lavoie ,  Zhengwen Li ,  Ahmet S. Ozcan ,  Filippos Papadatos ,  Chengwen Pei ,  Jian Yu

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L29/7833 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L23/535 ,  H01L29/1054 ,  H01L29/45 ,  H01L29/456 ,  H01L29/458 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7849

摘要： A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy.

摘要翻译： 提供一种形成半导体器件的方法，包括在半导体容纳表面上形成第一金属半导体合金，在第一金属半导体合金上形成电介质层，在电介质层中形成开口以提供第一金属半导体 合金，并且在第一金属半导体合金的暴露表面上形成第二金属半导体合金。 在另一个实施例中，该方法包括在半导体衬底的沟道区上形成栅极结构，在至少源极区和漏极区上形成电介质层，在电介质层中形成开口以提供暴露表面，半导体衬底 在所述半导体衬底的暴露表面上形成第一金属半导体合金，并在所述第一金属半导体合金上形成第二金属半导体合金。

公开(公告)号：US20120187460A1

公开(公告)日：2012-07-26

申请号：US13013081

申请日：2011-01-25

申请人： Christian Lavoie ,  Zhengwen Li ,  Ahmet S. Ozcan ,  Filippos Papadatos ,  Chengwen Pei ,  Jian Yu

发明人： Christian Lavoie ,  Zhengwen Li ,  Ahmet S. Ozcan ,  Filippos Papadatos ,  Chengwen Pei ,  Jian Yu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L23/535 ,  H01L29/1054 ,  H01L29/45 ,  H01L29/456 ,  H01L29/458 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7849

摘要： A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy.

摘要翻译： 提供一种形成半导体器件的方法，包括在半导体容纳表面上形成第一金属半导体合金，在第一金属半导体合金上形成电介质层，在电介质层中形成开口以提供第一金属半导体 合金，并且在第一金属半导体合金的暴露表面上形成第二金属半导体合金。 在另一个实施例中，该方法包括在半导体衬底的沟道区上形成栅极结构，在至少源极区和漏极区上形成电介质层，在电介质层中形成开口以提供暴露表面，半导体衬底 在所述半导体衬底的暴露表面上形成第一金属半导体合金，并在所述第一金属半导体合金上形成第二金属半导体合金。

公开(公告)号：US08916435B2

公开(公告)日：2014-12-23

申请号：US13228767

申请日：2011-09-09

申请人： Zhengwen Li ,  Damon B. Farmer ,  Michael P. Chudzik ,  Keith Kwong Hon Wong ,  Jian Yu ,  Zhen Zhang ,  Chengwen Pei

发明人： Zhengwen Li ,  Damon B. Farmer ,  Michael P. Chudzik ,  Keith Kwong Hon Wong ,  Jian Yu ,  Zhen Zhang ,  Chengwen Pei

IPC分类号： H01L21/8242 ,  H01L27/12 ,  H01L27/108 ,  H01L49/02 ,  H01L21/84 ,  H01L29/94

CPC分类号： H01L27/10829 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/945

摘要： A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.

摘要翻译： 提供一种存储器件和形成存储器件的方法，其包括具有金属半导体合金的下电极的电容器。 在一个实施例中，存储器件包括存在于半导体衬底中的沟槽，其包括在掩埋介电层顶部上的绝缘（SOI）半导体层，其中所述掩埋介电层位于基底半导体层的顶部。 电容器存在于沟槽中，其中电容器包括金属半导体合金的下电极，其具有与基底半导体层的上表面自对准的上边缘，高k电介质节点层和上层 金属电极。 存储器件还包括与电容器电连通的传输晶体管。

公开(公告)号：US08896088B2

公开(公告)日：2014-11-25

申请号：US13095164

申请日：2011-04-27

申请人： Yan Zun Li ,  Zhengwen Li ,  Chengwen Pei ,  Jian Yu

发明人： Yan Zun Li ,  Zhengwen Li ,  Chengwen Pei ,  Jian Yu

IPC分类号： H01L23/52 ,  H01L21/82 ,  H01L21/84 ,  H01L23/525 ,  H01L27/12 ,  G11C17/16

CPC分类号： H01L23/62 ,  G11C17/16 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76886 ,  H01L21/823814 ,  H01L21/84 ,  H01L23/5256 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact. The electrical fuse has a link within the substrate electrically interconnecting the anode contact and the cathode contact. The link comprises a semiconductor layer and a silicide layer. The silicide layer extends beyond the anode contact. An opposite end of the silicide layer extends beyond the cathode contact. A silicon germanium region is embedded in the semiconductor layer under the silicide layer, between the anode contact and the cathode contact.

摘要翻译： 电熔丝在半导体衬底的表面上具有阳极接触。 电熔丝在半导体衬底的与阳极接触件间隔开的表面上具有阴极接触。 电熔丝在衬底内具有连接阳极接触件和阴极接触件的连接。 该连接件包括半导体层和硅化物层。 硅化物层延伸超过阳极接触。 硅化物层的另一端延伸超过阴极接触。 在硅化物层之下的阳极接触和阴极接触之间的半导体层中嵌入硅锗区。

公开(公告)号：US20120261804A1

公开(公告)日：2012-10-18

申请号：US13087915

申请日：2011-04-15

申请人： Junjun Li ,  Zhengwen Li ,  Chengwen Pei ,  Jian Yu

发明人： Junjun Li ,  Zhengwen Li ,  Chengwen Pei ,  Jian Yu

IPC分类号： H01L29/06 ,  H01L21/22 ,  B82Y99/00

CPC分类号： H01L29/861 ,  H01L21/76256 ,  H01L27/0255

摘要： A diode structure, formed under a buried dielectric layer of a silicon on insulator (SOI), method of manufacturing the same and design structure thereof are provided. In an embodiment the p-n junction of the diode structure can be advantageously arranged in a vertical orientation. The cathode comprises an N+ epitaxial layer formed upon a P-type substrate. The anode comprises an active region of the P-substrate. Contacts to the cathode and anode are formed through the buried dielectric layer. Contact to the anode is accomplished via a deep trench filled with a conductive plug. The deep trench also provides electrical isolation for the cathode (as well as p-n junction). Advantageously, embodiments of the present invention may be formed during formation of other structures which also include trenches (for example, deep trench capacitors) in order to reduce process steps required to form the diode structure under the buried dielectric layer of the SOI substrate.

摘要翻译： 提供了一种二极管结构，其形成在绝缘体上的绝缘体（SOI）的埋置介质层下，其制造方法及其设计结构。 在一个实施例中，二极管结构的p-n结可以有利地以垂直取向布置。 阴极包括在P型衬底上形成的N +外延层。 阳极包括P基底的有源区。 通过埋入介电层形成与阴极和阳极的接触。 通过填充有导电插塞的深沟槽实现与阳极的接触。 深沟槽还为阴极（以及p-n结）提供电隔离。 有利地，本发明的实施例可以在形成其它结构的过程中形成，这些结构还包括沟槽（例如，深沟槽电容器），以便减少在SOI衬底的埋置介质层下形成二极管结构所需的工艺步骤。

公开(公告)号：US08981523B2

公开(公告)日：2015-03-17

申请号：US13419877

申请日：2012-03-14

申请人： Yan Zun Li ,  Zhengwen Li ,  Chengwen Pei ,  Jian Yu

发明人： Yan Zun Li ,  Zhengwen Li ,  Chengwen Pei ,  Jian Yu

IPC分类号： H01L23/52 ,  H01L23/525 ,  H01L23/532 ,  H01L27/115

CPC分类号： H01L23/5256 ,  H01L23/53204 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming an electrically programmable fuse (e-fuse) structure and the e-fuse structure are disclosed. Various embodiments of forming the e-fuse structure include: forming a dummy poly gate structure to contact a surface of a silicon structure, the dummy poly gate structure extending only a part of a length of the silicon structure; and converting an unobstructed portion of the surface of the silicon structure to silicide to form a thinned strip of the silicide between two end regions.

摘要翻译： 公开了形成电可编程熔丝（e熔丝）结构和电熔体结构的方法。 形成e熔丝结构的各种实施例包括：形成虚拟多晶硅结构以接触硅结构的表面，所述虚设多晶硅结构仅延伸所述硅结构的长度的一部分; 以及将所述硅结构的表面的无障碍部分转化为硅化物以在两个端部区域之间形成所述硅化物的薄化带。

公开(公告)号：US20130241031A1

公开(公告)日：2013-09-19

申请号：US13419877

申请日：2012-03-14

申请人： Yan Zun Li ,  Zhengwen Li ,  Chengwen Pei ,  Jian Yu

发明人： Yan Zun Li ,  Zhengwen Li ,  Chengwen Pei ,  Jian Yu

IPC分类号： H01L23/525 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L23/53204 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming an electrically programmable fuse (e-fuse) structure and the e-fuse structure are disclosed. Various embodiments of forming the e-fuse structure include: forming a dummy poly gate structure to contact a surface of a silicon structure, the dummy poly gate structure extending only a part of a length of the silicon structure; and converting an unobstructed portion of the surface of the silicon structure to silicide to form a thinned strip of the silicide between two end regions.

摘要翻译： 公开了形成电可编程熔丝（e熔丝）结构和电熔体结构的方法。 形成e熔丝结构的各种实施例包括：形成虚拟多晶硅结构以接触硅结构的表面，所述虚设多晶硅结构仅延伸所述硅结构的长度的一部分; 以及将所述硅结构的表面的无障碍部分转化为硅化物以在两个端部区域之间形成所述硅化物的薄化带。

公开(公告)号：US20130062677A1

公开(公告)日：2013-03-14

申请号：US13228767

申请日：2011-09-09

申请人： Zhengwen Li ,  Damon B. Farmer ,  Michael P. Chudzik ,  Keith Kwong Hon Wong ,  Jian Yu ,  Zhen Zhang ,  Chengwen Pei

发明人： Zhengwen Li ,  Damon B. Farmer ,  Michael P. Chudzik ,  Keith Kwong Hon Wong ,  Jian Yu ,  Zhen Zhang ,  Chengwen Pei

IPC分类号： H01L21/20 ,  H01L27/06

CPC分类号： H01L27/10829 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/945

摘要： A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.

摘要翻译： 提供一种存储器件和形成存储器件的方法，其包括具有金属半导体合金的下电极的电容器。 在一个实施例中，存储器件包括存在于半导体衬底中的沟槽，其包括在掩埋介电层顶部上的绝缘（SOI）半导体层，其中所述掩埋介电层位于基底半导体层的顶部。 电容器存在于沟槽中，其中电容器包括金属半导体合金的下电极，其具有与基底半导体层的上表面自对准的上边缘，高k电介质节点层和上层 金属电极。 存储器件还包括与电容器电连通的传输晶体管。

公开(公告)号：US20120119302A1

公开(公告)日：2012-05-17

申请号：US12944018

申请日：2010-11-11

申请人： Chengwen Pei ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Jian Yu

发明人： Chengwen Pei ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Jian Yu

IPC分类号： H01L23/532 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L21/76879 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/76805 ,  H01L23/485 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer.An interconnect is present within the via opening. A metal semiconductor alloy contact is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.

摘要翻译： 提供一种电结构，其包括存在于半导体衬底上的电介质层和通过电介质层存在的通路开口。 在通孔开口内存在互连。 在半导体衬底中存在金属半导体合金接触。 金属半导体合金触点具有由相对于通孔开口的中心线的凸曲面限定的周长。 限定金属半导体合金触点的凸曲率的端点与通孔开口的侧壁，互连的侧壁和半导体衬底的上表面之间的界面对准。

公开(公告)号：US20120104469A1

公开(公告)日：2012-05-03

申请号：US12912963

申请日：2010-10-27

申请人： Zhengwen Li ,  Dechao Guo ,  Randolph F. Knarr ,  Chengwen Pei ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong ,  Jian Yu ,  Jun Yuan

发明人： Zhengwen Li ,  Dechao Guo ,  Randolph F. Knarr ,  Chengwen Pei ,  Gan Wang ,  Yanfeng Wang ,  Keith Kwong Hon Wong ,  Jian Yu ,  Jun Yuan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/42368 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/78 ,  H01L29/7833

摘要： In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

摘要翻译： 在替代栅极方案中，连续材料层沉积在栅极腔中的底表面和侧壁表面上。 去除连续材料层的垂直部分以形成垂直部分不延伸到栅极腔的顶部的栅极部件。 栅组件可以用作栅极电介质或功函数金属部分，以形成增强替代栅极场效应晶体管的性能的栅极结构。