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5 条记录 (耗时 0.022 秒)

    Reconfigurable architecture for decoding telecommunications signals
    1.
    发明授权
    Reconfigurable architecture for decoding telecommunications signals 有权
    用于解码电信信号的可重构架构

    公开(公告)号：US07127664B2

    公开(公告)日：2006-10-24

    申请号：US09908003

    申请日：2001-07-18

    申请人： Christopher J. Nicol ,  Mark Andrew Bickerstaff ,  Bing Xu ,  Ran-Hong Yan

    发明人： Christopher J. Nicol ,  Mark Andrew Bickerstaff ,  Bing Xu ,  Ran-Hong Yan

    IPC分类号： H03M13/00

    CPC分类号： H03M13/3922 ,  H03M13/2957 ,  H03M13/3905 ,  H03M13/3927 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6502 ,  H03M13/6505 ,  H03M13/6508 ,  H03M13/6511 ,  H03M13/6513 ,  H03M13/6516 ,  H03M13/6566 ,  H04L1/0052 ,  H04L1/0054 ,  H04L1/0055

    摘要： The present invention discloses a single unified decoder for performing both convolutional decoding and turbo decoding in the one architecture. The unified decoder can be partitioned dynamically to perform required decoding operations on varying numbers of data streams at different throughput rates. It also supports simultaneous decoding of voice (convolutional decoding) and data (turbo decoding) streams. This invention forms the basis of a decoder that can decode all of the standards for TDMA, IS-95, GSM, GPRS, EDGE, UMTS, and CDMA2000. Processors are stacked together and interconnected so that they can perform separately as separate decoders or in harmony as a single high speed decoder. The unified decoder architecture can support multiple data streams and multiple voice streams simultaneously. Furthermore, the decoder can be dynamically partitioned as required to decode voice streams for different standards.

    摘要翻译： 本发明公开了一种用于在一种架构中执行卷积解码和turbo解码的单一统一解码器。 统一解码器可以动态分区，以不同吞吐率对不同数量的数据流执行所需的解码操作。 它还支持语音（卷积解码）和数据（turbo解码）流的同时解码。 本发明构成了可解码TDMA，IS-95，GSM，GPRS，EDGE，UMTS和CDMA2000的所有标准的解码器的基础。 处理器堆叠在一起并互连，使得它们可以单独执行单独的解码器或与单个高速解码器协调。 统一的解码器架构可以同时支持多个数据流和多个语音流。 此外，解码器可以根据需要被动态分割，以解码用于不同标准的语音流。

    Fully scalable memory apparatus
    3.
    发明授权
    Fully scalable memory apparatus 失效
    完全可扩展的存储设备

    公开(公告)号：US5355345A

    公开(公告)日：1994-10-11

    申请号：US132068

    申请日：1993-10-04

    申请人： Alexander G. Dickinson ,  Christopher J. Nicol

    发明人： Alexander G. Dickinson ,  Christopher J. Nicol

    IPC分类号： G06F12/00 ,  G11C8/12 ,  G11C13/00

    CPC分类号： G11C8/12

    摘要： A memory is partitioned into rows and columns of memory blocks comprised of latches, sense amplifiers, and logic circuitry that form independent pipelines through which flow a) input addresses for memory access requests and b) data to be written into a specific memory cell within a memory block. The memory allows multiple data access requests in consecutive clock cycles to be pipelined in the rows and columns of memory blocks such that the memory clock speed is equal to the clock speed of a single memory block, independently of the memory size.

    摘要翻译： 存储器被划分成由锁存器，读出放大器和形成独立管线的逻辑电路组成的存储器块的行和列，流程a）用于存储器访问请求的输入地址，以及b）要写入到存储器访问请求内的特定存储器单元的数据 内存块 存储器允许在连续时钟周期中的多个数据访问请求在存储器块的行和列中被流水线化，使得存储器时钟速度等于单个存储器块的时钟速度，而与存储器大小无关。

    Power reduction in a multiprocessor digital signal processor based on processor load
    4.
    发明授权
    Power reduction in a multiprocessor digital signal processor based on processor load 有权
    基于处理器负载的多处理器数字信号处理器的功耗降低

    公开(公告)号：US6141762A

    公开(公告)日：2000-10-31

    申请号：US128030

    申请日：1998-08-03

    申请人： Christopher J. Nicol ,  Kanwar Jit Singh

    发明人： Christopher J. Nicol ,  Kanwar Jit Singh

    IPC分类号： G06F1/04 ,  G06F1/32 ,  G06F9/46 ,  G06F9/50 ,  G06F15/78 ,  G06F9/44

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/505 ,  G06F9/5094 ,  Y02B60/1217 ,  Y02B60/1285 ,  Y02B60/142 ,  Y02B60/144

    摘要： Improved operation of multi-processor chips is achieved by dynamically controlling processing load of chips and controlling, significantly greater than on/off granularity, the operating voltages of those chips so as to minimize overall power consumption. A controller in a multi-processor chip allocates tasks to the individual processors to equalize processing load among the chips, then the controller lowers the clock frequency on the chip to as low a level as possible while assuring proper operation, and finally reduces the supply voltage. Further improvement is possible by controlling the supply voltage of individual processing elements within the multi-processor chip, as well as controlling the supply voltage of other elements in the system within which the multi-processor chip operates.

    摘要翻译： 多处理器芯片的改进操作通过动态地控制芯片的处理负载并且显着地大于开/关粒度来控制这些芯片的工作电压，从而最大限度地降低整体功耗来实现。 多处理器芯片中的控制器将各个处理器的任务分配给各个处理器之间的均衡，然后控制器将芯片上的时钟频率降至尽可能低的水平，同时确保正确的运行，并最终降低电源电压 。 通过控制多处理器芯片内的各个处理元件的电源电压以及控制多处理器芯片在其中运行的系统中的其它元件的电源电压，可以进一步改进。