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1.发明授权Automatic gain control and tuned low noise amplifier for process-independent gain systems 失效用于过程无关增益系统的自动增益控制和调谐低噪声放大器公开(公告)号：US07471152B2
公开(公告)日：2008-12-30
申请号：US11273376
申请日：2005-11-14
IPC分类号： H03F3/04
CPC分类号： H03M1/0607 , G01R31/2884 , G01R31/31715 , G01R31/31721 , G01S19/235 , G01S19/34 , G01S19/35 , G06F1/08 , H03F3/189 , H03F2200/294 , H03F2200/372 , H03L7/099 , H03L7/10 , H03L7/18
摘要： A tuned low-noise amplifier is disclosed. A device in accordance with the present invention comprises a first current source, a second current source, a comparator, coupled to the first current source and the second current source, for providing a control signal, and a third current source, receiving the control signal and coupled to the tuned low-noise amplifier, wherein a current in the third current source is proportional to a current in the first current source and the second current source, where values of the first current source, the second current source, and the third current source are based on a quasi-Proportional-To-Absolute-Temperature (PTAT) curve.
摘要翻译： 公开了调谐低噪声放大器。 根据本发明的装置包括耦合到第一电流源和第二电流源的用于提供控制信号的第一电流源，第二电流源，比较器和接收控制信号的第三电流源 并且耦合到调谐低噪声放大器，其中第三电流源中的电流与第一电流源和第二电流源中的电流成比例，其中第一电流源，第二电流源和第三电流源的值 电流源基于准比例 - 绝对温度（PTAT）曲线。
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2.发明授权Method and apparatus for a temperature compensated phase locked loop supporting a continuous stream receiver in an integrated 失效用于温度补偿锁相环的方法和装置，其支持集成的连续流接收器公开(公告)号：US08521115B2
公开(公告)日：2013-08-27
申请号：US13369998
申请日：2012-02-09
申请人： Christopher R. Leon
发明人： Christopher R. Leon
摘要： An integrated circuit including a Phase Locked Loop (PLL) configured for use with a continuous stream receiver is disclosed. A control voltage line is configured to deliver a control voltage with a capacitive load delivered by a capacitor array to the control voltage based upon an add signal and a subtract signal. A threshold generator generates a high threshold voltage and a low threshold voltage using and including at least one process dependent resistor and at least two temperature and process dependent current sources. The PLL responds during calibration to the control voltage being above the high threshold voltage by asserting the add signal directing the capacitor array to increase the capacitive load on the control voltage line, and to the control voltage being below the low threshold voltage by asserting the subtract signal to decrease the capacitive load.
摘要翻译： 公开了一种集成电路，其包括被配置为与连续流接收器一起使用的锁相环（PLL）。 控制电压线被配置为基于加法信号和减法信号将由电容器阵列传递的电容性负载的控制电压传递到控制电压。 阈值发生器使用并包括至少一个过程相关电阻器和至少两个温度和过程相关电流源来产生高阈值电压和低阈值电压。 PLL在校准期间响应于高于高阈值电压的控制电压，通过断言引导电容器阵列的增加信号增加控制电压线上的电容性负载，并通过断言减法来控制电压低于低阈值电压 信号降低容性负载。
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3.发明授权公开(公告)号：US08350600B2
公开(公告)日：2013-01-08
申请号：US11271121
申请日：2005-11-10
申请人： Christopher R. Leon
发明人： Christopher R. Leon
IPC分类号： G06F1/08
CPC分类号： H03M1/0607 , G01R31/2884 , G01R31/31715 , G01R31/31721 , G01S19/235 , G01S19/34 , G01S19/35 , G06F1/08 , H03F3/189 , H03F2200/294 , H03F2200/372 , H03L7/099 , H03L7/10 , H03L7/18
摘要： A glitchless clock multiplexer controlled by an asynchronous select signal for use in GPS receivers is disclosed. A device in accordance with the present invention comprises a device for producing a clock signal, the clock signal being selected from a plurality of asynchronous frequency sources. A device in accordance with the present invention comprises a first frequency source, a second frequency source, a select signal, wherein the select signal is asynchronous with the first frequency source, and a multiplexer, which receives the first frequency source and the second frequency source, wherein the multiplexer selects as an output of the multiplexer one of the first frequency source and the second frequency source based on a value of the select signal, such that when the multiplexer switches between the first frequency source and the second frequency source, and between the second frequency source and the first frequency source, the transition is performed when the output of the multiplexer is at a logic low.
摘要翻译： 公开了一种由用于GPS接收机的异步选择信号控制的无干扰时钟复用器。 根据本发明的装置包括用于产生时钟信号的装置，所述时钟信号从多个异步频率源中选择。 根据本发明的装置包括第一频率源，第二频率源，选择信号，其中选择信号与第一频率源异步;以及多路复用器，其接收第一频率源和第二频率源 ，其中所述多路复用器基于所述选择信号的值，选择所述第一频率源和所述第二频率源中的多路复用器的输出，使得当所述多路复用器在所述第一频率源和所述第二频率源之间以及在 第二频率源和第一频率源，当多路复用器的输出处于逻辑低电平时执行转换。
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4.发明授权公开(公告)号：US08203393B1
公开(公告)日：2012-06-19
申请号：US12272149
申请日：2008-11-17
申请人： Christopher R. Leon
发明人： Christopher R. Leon
IPC分类号： H03K3/354
CPC分类号： H03K3/011
摘要： A voltage controlled oscillator having a temperature and process controlled output. A VCO in accordance with the present invention comprises a reference current source, a fixed current source, coupled in series with the reference current source, the fixed current source comprising a temperature independent current source, a third current source, coupled in parallel with the combination of the reference current source and the fixed current source, and an oscillator, coupled in series with the third current source, wherein a current used to control the oscillator is based on operating temperatures and processes of the reference current source and the third current source.
摘要翻译： 具有温度和过程控制输出的压控振荡器。 根据本发明的VCO包括与参考电流源串联耦合的参考电流源，固定电流源，固定电流源包括与温度无关的电流源，与组合并联耦合的第三电流源 参考电流源和固定电流源，以及与第三电流源串联耦合的振荡器，其中用于控制振荡器的电流基于参考电流源和第三电流源的操作温度和过程。
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公开(公告)号：US06798263B1
公开(公告)日：2004-09-28
申请号：US10304310
申请日：2002-11-25
申请人： Christopher R. Leon
发明人： Christopher R. Leon
IPC分类号： H03K3289
CPC分类号： H03K3/356139 , H03K3/356008
摘要： A differential latch circuit with a differential reset function includes a first arrangement of transistors configured to perform a latch function and a second arrangement of transistors, connected to the first arrangement of transistors, configured to perform a reset function. The first arrangement of transistors includes branches having three cascoded transistors, and the second arrangement of transistors includes branches having two cascoded transistors. This configuration enables the latch circuit to use lower power supply voltages relative to conventional latch circuits that require four more cascoded transistors.
摘要翻译： 具有差分复位功能的差分锁存电路包括被配置为执行锁存功能的晶体管的第一配置和连接到晶体管的第一配置的晶体管的第二配置，被配置为执行复位功能。 晶体管的第一布置包括具有三个级联晶体管的分支，并且晶体管的第二布置包括具有两个级联晶体管的分支。 这种配置使得锁存电路相对于需要四个更多级联晶体管的常规锁存电路使用较低的电源电压。
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6.发明申请METHOD AND APPARATUS FOR A TEMPERATURE COMPENSATED PHASE LOCKED LOOP SUPPORTING A CONTINUOUS STREAM RECEIVER IN AN INTEGRATED 失效在一体化中支持连续流水线接收器的温度补偿相位锁定环路的方法和装置公开(公告)号：US20120139594A1
公开(公告)日：2012-06-07
申请号：US13369998
申请日：2012-02-09
申请人： Christopher R. Leon
发明人： Christopher R. Leon
IPC分类号： H03L7/08
摘要： An integrated circuit including a Phase Locked Loop (PLL) configured for use with a continuous stream receiver is disclosed. A control voltage line is configured to deliver a control voltage with a capacitive load delivered by a capacitor array to the control voltage based upon an add signal and a subtract signal. A threshold generator generates a high threshold voltage and a low threshold voltage using and including at least one process dependent resistor and at least two temperature and process dependent current sources. The PLL responds during calibration to the control voltage being above the high threshold voltage by asserting the add signal directing the capacitor array to increase the capacitive load on the control voltage line, and to the control voltage being below the low threshold voltage by asserting the subtract signal to decrease the capacitive load.
摘要翻译： 公开了一种集成电路，其包括被配置为与连续流接收器一起使用的锁相环（PLL）。 控制电压线被配置为基于加法信号和减法信号将由电容器阵列传递的电容性负载的控制电压传递到控制电压。 阈值发生器使用并包括至少一个过程相关电阻器和至少两个温度和过程相关电流源来产生高阈值电压和低阈值电压。 PLL在校准期间响应于高于高阈值电压的控制电压，通过断言引导电容器阵列的增加信号增加控制电压线上的电容性负载，并通过断言减法来控制电压低于低阈值电压 信号降低容性负载。
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7.发明授权Method and apparatus for a temperature compensated phase locked loop supporting a continuous stream receiver in an integrated circuit 有权用于在集成电路中支持连续流接收器的温度补偿锁相环的方法和装置公开(公告)号：US08140040B1
公开(公告)日：2012-03-20
申请号：US12558388
申请日：2009-09-11
申请人： Christopher R. Leon
发明人： Christopher R. Leon
摘要： An integrated circuit including a Phase Locked Loop (PLL) configured for use with a continuous stream receiver is disclosed. A control voltage line is configured to deliver a control voltage with a capacitive load delivered by a capacitor array to the control voltage based upon an add signal and a subtract signal. A threshold generator generates a high threshold voltage and a low threshold voltage using and including at least one process dependent resistor and at least two temperature and process dependent current sources. The PLL responds during calibration to the control voltage being above the high threshold voltage by asserting the add signal directing the capacitor array to increase the capacitive load on the control voltage line, and to the control voltage being below the low threshold voltage by asserting the subtract signal to decrease the capacitive load.
摘要翻译： 公开了一种集成电路，其包括配置为与连续流接收器一起使用的锁相环（PLL）。 控制电压线被配置为基于加法信号和减法信号将由电容器阵列传递的电容性负载的控制电压传递到控制电压。 阈值发生器使用并包括至少一个过程相关电阻器和至少两个温度和过程相关电流源来产生高阈值电压和低阈值电压。 PLL在校准期间响应于高于高阈值电压的控制电压，通过断言引导电容器阵列的增加信号增加控制电压线上的电容性负载，并通过断言减法来控制电压低于低阈值电压 信号降低容性负载。
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8.发明申请公开(公告)号：US20080094108A1
公开(公告)日：2008-04-24
申请号：US11271121
申请日：2005-11-10
申请人： Christopher R. Leon
发明人： Christopher R. Leon
IPC分类号： G06F1/08
CPC分类号： H03M1/0607 , G01R31/2884 , G01R31/31715 , G01R31/31721 , G01S19/235 , G01S19/34 , G01S19/35 , G06F1/08 , H03F3/189 , H03F2200/294 , H03F2200/372 , H03L7/099 , H03L7/10 , H03L7/18
摘要： A glitchless clock multiplexer controlled by an asynchronous select signal for use in GPS receivers is disclosed. A device in accordance with the present invention comprises a device for producing a clock signal, the clock signal being selected from a plurality of asynchronous frequency sources. A device in accordance with the present invention comprises a first frequency source, a second frequency source, a select signal, wherein the select signal is asynchronous with the first frequency source, and a multiplexer, which receives the first frequency source and the second frequency source, wherein the multiplexer selects as an output of the multiplexer one of the first frequency source and the second frequency source based on a value of the select signal, such that when the multiplexer switches between the first frequency source and the second frequency source, and between the second frequency source and the first frequency source, the transition is performed when the output of the multiplexer is at a logic low.
摘要翻译： 公开了一种由用于GPS接收机的异步选择信号控制的无干扰时钟复用器。 根据本发明的装置包括用于产生时钟信号的装置，所述时钟信号从多个异步频率源中选择。 根据本发明的装置包括第一频率源，第二频率源，选择信号，其中选择信号与第一频率源异步;以及多路复用器，其接收第一频率源和第二频率源 ，其中所述多路复用器基于所述选择信号的值，选择所述第一频率源和所述第二频率源中的多路复用器的输出，使得当所述多路复用器在所述第一频率源和所述第二频率源之间以及在 第二频率源和第一频率源，当多路复用器的输出处于逻辑低电平时执行转换。
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