公开(公告)号：US08228704B2

公开(公告)日：2012-07-24

申请号：US12072401

申请日：2008-02-26

申请人： Chul-Hwan Choo ,  Hi-Choon Lee ,  Young-Yong Byun

发明人： Chul-Hwan Choo ,  Hi-Choon Lee ,  Young-Yong Byun

IPC分类号： G11C5/06

CPC分类号： H03L7/0812 ,  G11C5/02 ,  G11C5/04 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15311 ,  H03L7/0814 ,  H01L2224/0401

摘要： A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved.

摘要翻译： 提供半导体芯片封装和半导体芯片制造方法。 半导体芯片封装包括至少两个具有堆叠结构的半导体芯片，所述半导体芯片至少一个：共享由所述半导体芯片中的一个提供的直流发电电路的直流信号; 并且共享由具有DC发生电路的半导体芯片提供或由另一半导体芯片提供的DLL电路的DLL电路的DLL时钟信号。 可以减少功耗，共享DLL时钟是有效的。 此外，可以保证稳定的DC电源，并且可以提高修整范围和生产率的增加。

公开(公告)号：US20080204091A1

公开(公告)日：2008-08-28

申请号：US12072401

申请日：2008-02-26

申请人： Chul-Hwan Choo ,  Hi-Choon Lee ,  Young-Yong Byun

发明人： Chul-Hwan Choo ,  Hi-Choon Lee ,  Young-Yong Byun

IPC分类号： H03L7/08 ,  H01L23/12

CPC分类号： H03L7/0812 ,  G11C5/02 ,  G11C5/04 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15311 ,  H03L7/0814 ,  H01L2224/0401

摘要： A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved.

摘要翻译： 提供半导体芯片封装和半导体芯片制造方法。 半导体芯片封装包括至少两个具有堆叠结构的半导体芯片，所述半导体芯片至少一个：共享由所述半导体芯片中的一个提供的直流发电电路的直流信号; 并且共享由具有DC发生电路的半导体芯片提供或由另一半导体芯片提供的DLL电路的DLL电路的DLL时钟信号。 可以减少功耗，共享DLL时钟是有效的。 此外，可以保证稳定的DC电源，并且可以提高修整范围和生产率的增加。

公开(公告)号：US07477715B2

公开(公告)日：2009-01-13

申请号：US11623925

申请日：2007-01-17

申请人： Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

发明人： Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

IPC分类号： H03D3/24

CPC分类号： H03L7/0814 ,  H03K5/13 ,  H03K2005/00052

摘要： A delay-locked loop (DLL) circuit includes a standby signal generating circuit, a front stage circuit, and a back stage circuit. The standby signal generating circuit generates a first standby signal and a second standby signal in response to an active signal, a crock enable signal, a first column address strobe (CAS) latency signal, and a second CAS latency signal. The front stage circuit compares the phase of an external clock signal and the phase of a feedback signal and delays the external clock signal based on the phase difference between the external clock signal and the feedback signal to generate a first clock signal. The back stage circuit executes interpolation and duty-cycle correction on the first clock signal.

摘要翻译： 延迟锁定环路（DLL）电路包括备用信号发生电路，前级电路和后级电路。 待机信号发生电路响应于有效信号，一个使能信号，一个第一列地址选通（CAS）等待时间信号和一个第二CAS等待时间信号，产生第一待机信号和第二备用信号。 前级电路将外部时钟信号的相位与反馈信号的相位进行比较，并且基于外部时钟信号和反馈信号之间的相位差来延迟外部时钟信号以产生第一时钟信号。 后级电路对第一时钟信号执行内插和占空比校正。

公开(公告)号：US20070176657A1

公开(公告)日：2007-08-02

申请号：US11623925

申请日：2007-01-17

申请人： Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

发明人： Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/13 ,  H03K2005/00052

摘要： A delay-locked loop (DLL) circuit includes a standby signal generating circuit, a front stage circuit, and a back stage circuit. The standby signal generating circuit generates a first standby signal and a second standby signal in response to an active signal, a crock enable signal, a first column address strobe (CAS) latency signal, and a second CAS latency signal. The front stage circuit compares the phase of an external clock signal and the phase of a feedback signal and delays the external clock signal based on the phase difference between the external clock signal and the feedback signal to generate a first clock signal. The back stage circuit executes interpolation and duty-cycle correction on the first clock signal.

摘要翻译： 延迟锁定环路（DLL）电路包括备用信号发生电路，前级电路和后级电路。 待机信号发生电路响应于有效信号，一个使能信号，一个第一列地址选通（CAS）等待时间信号和一个第二CAS等待时间信号，产生第一待机信号和第二备用信号。 前级电路将外部时钟信号的相位与反馈信号的相位进行比较，并且基于外部时钟信号和反馈信号之间的相位差来延迟外部时钟信号以产生第一时钟信号。 后级电路对第一时钟信号执行内插和占空比校正。

公开(公告)号：US20080046788A1

公开(公告)日：2008-02-21

申请号：US11561023

申请日：2006-11-17

申请人： Hi-Choon Lee ,  Sung-Bum Cho

发明人： Hi-Choon Lee ,  Sung-Bum Cho

IPC分类号： G11C29/00

CPC分类号： G11C29/14 ,  G11C29/1201 ,  G11C2029/2602

摘要： The present invention provides a semiconductor memory device comprising a memory cell array including a plurality of memory regions, an address decoding portion for decoding an address applied from an external portion for simultaneously selecting all of the plurality of memory regions during a test read operation, a data IO control portion for receiving test pattern data and writing the test pattern data to each of the plurality of memory regions during a test write operation, and reading the test pattern data from one of the plurality of memory regions and outputting the test pattern data during the test read operation, a data IO portion for receiving the test pattern data from the external portion and applying the test pattern data to the data IO control portion during the test write operation, and receiving the test pattern data output from the data IO control portion and conditionally outputting the test pattern data as test status data to the external portion in response to an output control signal during the test read operation, and a test control signal generating portion for comparing the test pattern data read from the plurality of memory regions to generate the output control signal for conditionally outputting the test pattern data as the test status data during the test read operation.

摘要翻译： 本发明提供一种包括存储单元阵列的半导体存储器件，该存储单元阵列包括多个存储区域，地址解码部分，用于解码从外部部分施加的地址，用于在测试读取操作期间同时选择所有多个存储器区域; 数据IO控制部分，用于在测试写入操作期间接收测试图案数据并将测试图案数据写入到多个存储器区域中的每一个，并且从多个存储区域中的一个读取测试图案数据，并在 测试读取操作，用于从外部部分接收测试图案数据并在测试写入操作期间将测试图案数据应用于数据IO控制部分的数据IO部分，以及从数据IO控制部分输出的测试图案数据 并响应于外部条件将测试图形数据作为测试状态数据输出到外部部分 在测试读取操作期间放置控制信号，以及测试控制信号生成部分，用于比较从多个存储区域读取的测试图形数据，以产生输出控制信号，用于有条件地输出测试模式数据作为测试状态数据 读操作。

公开(公告)号：US20070165470A1

公开(公告)日：2007-07-19

申请号：US11651973

申请日：2007-01-11

申请人： Jin-Hyung Cho ,  Hi-Choon Lee

发明人： Jin-Hyung Cho ,  Hi-Choon Lee

IPC分类号： G11C29/00

CPC分类号： G11C29/12 ,  G01R31/3004 ,  G11C29/006 ,  G11C29/12005 ,  G11C2029/1204

摘要： A semiconductor device for generating a test voltage for a wafer burn-in test and method thereof is disclosed. To generate the test voltage for a wafer burn-in test, a control signal may be generated in response to a supply voltage from an external wafer burn-in test device. A supplementary voltage may be generated in response to the control signal by using an internal voltage driving circuit. The test voltage may be generated by combining the supply voltage and the supplementary voltage.

摘要翻译： 公开了一种用于生成晶片老化测试的测试电压的半导体器件及其方法。 为了产生用于晶片老化测试的测试电压，可以响应于来自外部晶片老化测试装置的电源电压而产生控制信号。 可以通过使用内部电压驱动电路来响应于控制信号产生辅助电压。 可以通过组合电源电压和辅助电压来产生测试电压。

公开(公告)号：US08010765B2

公开(公告)日：2011-08-30

申请号：US11775780

申请日：2007-07-10

申请人： Joo-Sun Choi ,  Won-Chang Jung ,  Hi-Choon Lee ,  Sung-Min Yim ,  Chul-Woo Park ,  Won-Il Bae

发明人： Joo-Sun Choi ,  Won-Chang Jung ,  Hi-Choon Lee ,  Sung-Min Yim ,  Chul-Woo Park ,  Won-Il Bae

IPC分类号： G06F12/00

CPC分类号： G11C7/1045 ,  G11C7/1072

摘要： In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control signal having a logic level that varies depending on whether or not an output order of burst data is reordered. The latency control unit may control a latency value in response to the latency control signal. The semiconductor memory device and the method of controlling the latency value responsive to a reordering of the burst data allow for an optimally fast memory access time.

摘要翻译： 在一个实施例中，半导体存储器件包括响应于突发数据的输出顺序是否被重新排序而被控制的时钟等待时间。 半导体存储器件可以包括控制单元和等待时间控制单元。 控制单元可以生成具有根据突发数据的输出顺序是否被重新排列而变化的逻辑电平的等待时间控制信号。 延迟控制单元可以响应于等待时间控制信号来控制等待时间值。 半导体存储器件和响应于突发数据的重排序来控制延迟值的方法允许最佳的快速存储器存取时间。

公开(公告)号：US07487414B2

公开(公告)日：2009-02-03

申请号：US11500126

申请日：2006-08-07

申请人： Hi-Choon Lee

发明人： Hi-Choon Lee

IPC分类号： G11C29/00

CPC分类号： G11C29/40 ,  G11C29/44 ,  G11C2029/2602

摘要： An integrated circuit device includes a test circuit and at least one flag generator circuit. The test circuit is configured to generate first and second sets of test results in parallel in response to a memory test operation. The first and second sets of test results respectively correspond to first and second memory banks. The test circuit is further configured to merge respective ones of the first set of test results with respective ones of the second set of test results to provide a set of merged test results to respective ones of a set of output terminals of the integrated circuit device. The at least one flag generator circuit is configured to generate a first flag signal that indicates a presence of at least one memory test error in the first set of test results, and a second flag signal that indicates a presence of at least one memory test error in the second set of test results. Based on the set of merged test results and the first and second flag signals, the test circuit may determine which of the memory blocks of the first and second memory banks includes a defective memory cell therein. Related methods are also discussed.

摘要翻译： 集成电路装置包括测试电路和至少一个标志发生器电路。 测试电路被配置为响应于存储器测试操作并行地产生第一和第二组测试结果。 第一组和第二组测试结果分别对应于第一和第二存储体。 测试电路还被配置为将第一组测试结果中的相应测试结果与第二组测试结果中的相应测试结果合并，以向集成电路设备的一组输出终端中的相应测试结果提供一组合并的测试结果。 所述至少一个标志发生器电路被配置为产生指示在所述第一组测试结果中存在至少一个存储器测试错误的第一标志信号，以及指示存在至少一个存储器测试错误的第二标志信号 在第二组测试结果中。 基于合并的测试结果集合和第一和第二标志信号，测试电路可以确定第一和第二存储器组中的哪些存储块包括其中的有缺陷的存储单元。 还讨论了相关方法。

公开(公告)号：US06785171B2

公开(公告)日：2004-08-31

申请号：US10237665

申请日：2002-09-10

申请人： Hi-Choon Lee ,  Byoung-Ju Kim

发明人： Hi-Choon Lee ,  Byoung-Ju Kim

IPC分类号： G11C700

CPC分类号： G11C29/808 ,  G11C29/785

摘要： A semiconductor memory device includes a plurality of sub-wordlines, a plurality of sub-wordlines corresponding a redundancy main wordline, a plurality of redundancy memory cells each being coupled to each of the redundancy sub-wordlines, and a redundancy control circuit for disabling the main wordline selector when among the sub-wordlines, a sub-wordline to which a defective memory cell is coupled is addressed, and for controlling the sub-wordline to be replaced by the redundancy main wordline. The number of the redundancy sub-wordlines coupled to the redundancy main wordline is smaller than the number of the sub-wordlines coupled to the main wordline. Therefore, when among the sub-wordlines coupled to the main wordline, a sub-wordline to which a normal main memory cell is coupled is addressed, the main wordline selector is enabled to improve a redundancy flexibility and reduce a circuit area.

摘要翻译： 半导体存储器件包括多个子字线，对应于冗余主字线的多个子字线，每个冗余存储器单元分别耦合到每个冗余子字线，以及冗余控制电路，用于禁用 主字线选择器在子字线之间寻址与缺陷存储器单元耦合的子字线，并且用于控制副字线被冗余主字线替代。 耦合到冗余主字线的冗余子字线的数量小于耦合到主字线的子字线的数量。 因此，当耦合到主字线的子字线中，寻址与正常主存储器单元耦合的子字线时，主字选择器能够提高冗余灵活性并减少电路面积。

公开(公告)号：US07800961B2

公开(公告)日：2010-09-21

申请号：US12260206

申请日：2008-10-29

申请人： Chris Ji Yoon Son ,  Hi-Choon Lee

发明人： Chris Ji Yoon Son ,  Hi-Choon Lee

IPC分类号： G11C16/04

CPC分类号： G11C8/08 ,  G11C11/406 ,  G11C11/4087 ,  G11C2211/4065 ,  G11C2211/4067

摘要： A word line driver for use in a semiconductor memory device includes a boosted voltage generator, a sub word line driver and a main word line driver. The boosted voltage generator generates a boosted voltage by receiving an internal power supply voltage and pumping electric charge. The sub word line driver receives the internal power supply voltage and activates a boosted voltage control signal after supplying the internal power supply voltage to a boost node in a command operating mode. The main word line driver enables a word line by supplying the boosted voltage to the boost node in response to the boosted voltage control signal in a normal operating mode, and enables the word line with the boosted voltage after boosting the word line to the internal power supply voltage by changing the boost node from the internal power supply voltage to the boosted voltage in the command operating mode.

摘要翻译： 用于半导体存储器件的字线驱动器包括升压电压发生器，子字线驱动器和主字线驱动器。 升压电压发生器通过接收内部电源电压和泵送电荷而产生升压电压。 子字线驱动器接收内部电源电压，并且在命令操作模式下将内部电源电压提供给升压节点之后激活升压电压控制信号。 主字符驱动器通过在正常工作模式下响应于升压电压控制信号而将升压电压提供给升压节点来实现字线，并且在将字线升压到内部电源之后使得具有升压电压的字线 在指令运行模式下，通过将升压节点从内部电源电压改变为升压电压来提供电压。