公开(公告)号：US07259978B2

公开(公告)日：2007-08-21

申请号：US11221684

申请日：2005-09-08

申请人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

发明人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C8/14

摘要： A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.

摘要翻译： 半导体存储器件可以包括存储单元阵列，位线读出放大器，子字线驱动器和电极。 存储单元阵列可以包括连接在子字线和位线对之间并具有响应于发送到子字线和列选择信号线的信号而被选择的存储器单元的子存储单元阵列。 位线读出放大器可以被配置为感测和放大位线对的数据。 子字线驱动器可以被配置为组合从字选择信号线发送的信号和从主字线发送的信号，以选择子字线。 此外，存储单元阵列可以被配置为在位线对和本地数据线对之间传输数据，并且在本地数据线对和全局数据线对之间传送数据。 电极可以被配置为覆盖整个存储单元阵列并施加存储单元所需的电压。 局部数据线对可以以与子字线相同的方向布置在电极上方的第一层上。 列选择信号线和全局数据线对可以以与位线相同的方向布置在电极上方的第二层上。 字选择信号线和主字线可以沿与子字线相同的方向布置在电极上方的第三层上。 还讨论了信号线布置的相关方法。

公开(公告)号：US20060056218A1

公开(公告)日：2006-03-16

申请号：US11221684

申请日：2005-09-08

申请人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

发明人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C8/14

摘要： A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.

摘要翻译： 半导体存储器件可以包括存储单元阵列，位线读出放大器，子字线驱动器和电极。 存储单元阵列可以包括连接在子字线和位线对之间并具有响应于发送到子字线和列选择信号线的信号而被选择的存储器单元的子存储单元阵列。 位线读出放大器可以被配置为感测和放大位线对的数据。 子字线驱动器可以被配置为组合从字选择信号线发送的信号和从主字线发送的信号，以选择子字线。 此外，存储单元阵列可以被配置为在位线对和本地数据线对之间传输数据，并且在本地数据线对和全局数据线对之间传送数据。 电极可以被配置为覆盖整个存储单元阵列并施加存储单元所需的电压。 局部数据线对可以以与子字线相同的方向布置在电极上方的第一层上。 列选择信号线和全局数据线对可以以与位线相同的方向布置在电极上方的第二层上。 字选择信号线和主字线可以沿着与子字线相同的方向布置在电极上方的第三层上。 还讨论了信号线布置的相关方法。

公开(公告)号：US07710807B2

公开(公告)日：2010-05-04

申请号：US12021762

申请日：2008-01-29

申请人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

发明人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C11/406 ,  G11C11/4091 ,  G11C2211/4065

摘要： A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. This electrically coupling is provided so that each of the first pair of MOS transistors has a first source/drain terminal electrically connected to a corresponding one of the pair of sense bit lines and the second source/drain terminals of the first pair of MOS transistors are electrically connected together. The first pair of MOS transistors of first conductivity type is configured to have different threshold voltages or support different threshold voltage biasing. The second MOS sense amplifier has a first pair of MOS transistors of second conductivity type therein, which are electrically coupled across the pair of sense bit lines.

摘要翻译： 感测放大器包括一对感测位线和第一和第二MOS读出放大器。 第一MOS读出放大器在其中具有第一导电类型的第一对MOS晶体管，其电耦合在该对感测位线之间。 该电耦合被提供为使得第一对MOS晶体管中的每一个具有电连接到该对感测位线中的相应一个和第一对MOS晶体管的第二源极/漏极端子的第一源极/漏极端子 电连接在一起。 第一导电类型的第一对MOS晶体管被配置为具有不同的阈值电压或支持不同的阈值电压偏置。 第二MOS读出放大器具有第一对第二导电类型的MOS晶体管，它们在一对感测位线之间电耦合。

公开(公告)号：US07345939B2

公开(公告)日：2008-03-18

申请号：US11185351

申请日：2005-07-20

申请人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

发明人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C11/406 ,  G11C11/4091 ,  G11C2211/4065

摘要： A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. This electrically coupling is provided so that each of the first pair of MOS transistors has a first source/drain terminal electrically connected to a corresponding one of the pair of sense bit lines and the second source/drain terminals of the first pair of MOS transistors are electrically connected together. The first pair of MOS transistors of first conductivity type are configured to have different threshold voltages or support different threshold voltage biasing. The second MOS sense amplifier has a first pair of MOS transistors of second conductivity type therein, which are electrically coupled across the pair of sense bit lines.

摘要翻译： 感测放大器包括一对感测位线和第一和第二MOS读出放大器。 第一MOS读出放大器在其中具有第一导电类型的第一对MOS晶体管，其电耦合在该对感测位线之间。 该电耦合被提供为使得第一对MOS晶体管中的每一个具有电连接到该对感测位线中的相应一个和第一对MOS晶体管的第二源极/漏极端子的第一源极/漏极端子 电连接在一起。 第一导电类型的第一对MOS晶体管被配置为具有不同的阈值电压或支持不同的阈值电压偏置。 第二MOS读出放大器具有第一对第二导电类型的MOS晶体管，它们在一对感测位线之间电耦合。

公开(公告)号：US20060023537A1

公开(公告)日：2006-02-02

申请号：US11185351

申请日：2005-07-20

申请人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

发明人： Hyun-Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C11/406 ,  G11C11/4091 ,  G11C2211/4065

摘要： A semiconductor memory device and a bit line sensing method thereof are disclosed. The semiconductor memory device includes a first memory cell connected between a first word line accessed by a first address and an inverted bit line; a second memory cell connected between a second word line accessed by a second address and a bit line; a first type sense amplifier serially connected between the bit line and the inverted bit line and having a first type first MOS transistor sensing the inverted bit line and a first type second MOS transistor sensing the bit line if a first enable signal of a first voltage is applied; a second type first sense amplifier serially connected between the bit line and the inverted bit line and having a second type first MOS transistor sensing the inverted bit line and a second type second MOS transistor sensing the bit line if a second enable signal of a second voltage is applied, wherein the second type first MOS transistor has a better sensing ability than the second type second MOS transistor; and a second type second sense amplifier serially connected between the bit line and the inverted bit line and having a second type third MOS transistor sensing the inverted bit line and a second type fourth MOS transistor sensing the bit line if a third enable signal of the second voltage is applied, wherein the second type fourth MOS transistor has a better sensing ability than the second type third MOS transistor.

摘要翻译： 公开了一种半导体存储器件及其位线检测方法。 半导体存储器件包括连接在由第一地址和反向位线访问的第一字线之间的第一存储器单元; 连接在由第二地址访问的第二字线和位线之间的第二存储器单元; 第一类型读出放大器串联连接在位线和反相位线之间，并且具有感测反向位线的第一类型第一MOS晶体管和感测位线的第一类型第二MOS晶体管，如果第一电压的第一使能信号为 应用; 串联连接在位线和反相位线之间的第二类型的第一读出放大器，并且具有检测反相位线的第二类型的第一MOS晶体管和感测位线的第二类型的第二MOS晶体管，如果第二电压的第二使能信号 其中所述第二类型的第一MOS晶体管具有比所述第二类型的第二MOS晶体管更好的感测能力; 以及第二类型的第二读出放大器，其串联连接在位线和反相位线之间，并且具有感测反转位线的第二类型的第三MOS晶体管和感测位线的第二类型的第四MOS晶体管，如果第二个 施加电压，其中第二类型的第四MOS晶体管具有比第二类型的第三MOS晶体管更好的感测能力。

公开(公告)号：US06452828B1

公开(公告)日：2002-09-17

申请号：US09886202

申请日：2001-06-20

申请人： Sang-Seok Kang ,  Jong-Hyun Choi ,  Jong-Eon Lee

发明人： Sang-Seok Kang ,  Jong-Hyun Choi ,  Jong-Eon Lee

IPC分类号： G11C506

CPC分类号： G11C11/4085 ,  G11C8/08

摘要： Disclosed is a dynamic random access memory (DRAM) device having word line low voltage supply lines for driving word lines in a mesh structure. The DRAM device includes a plurality of cell arrays each of which is formed of memory cells coupled to word lines and bit lines in a matrix. The memory device further includes regions of sense amplifiers disposed between the cell arrays arranged along the row direction, regions of word line drivers disposed between the cell arrays arranged along the column direction, conjunction regions disposed at positions adjacent to the regions of the sense amplifiers and word line drivers, and a plurality of word line low voltage supply lines disposed on the conjunction regions. The word line low voltage supply lines are electrically interconnected for each other at least on the conjunction regions. According to the layout arrangement, loadings of the word line low voltage supply lines are almost equally distributed, and thereby word line low noise are decreased.

公开(公告)号：US20080144414A1

公开(公告)日：2008-06-19

申请号：US12021762

申请日：2008-01-29

申请人： Hyun Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

发明人： Hyun Seok Lee ,  Jong-Hyun Choi ,  Ki-Chul Chun ,  Jong-Eon Lee

IPC分类号： G11C7/06

CPC分类号： G11C7/065 ,  G11C11/406 ,  G11C11/4091 ,  G11C2211/4065

摘要： A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. This electrically coupling is provided so that each of the first pair of MOS transistors has a first source/drain terminal electrically connected to a corresponding one of the pair of sense bit lines and the second source/drain terminals of the first pair of MOS transistors are electrically connected together. The first pair of MOS transistors of first conductivity type is configured to have different threshold voltages or support different threshold voltage biasing. The second MOS sense amplifier has a first pair of MOS transistors of second conductivity type therein, which are electrically coupled across the pair of sense bit lines.

摘要翻译： 感测放大器包括一对感测位线和第一和第二MOS读出放大器。 第一MOS读出放大器在其中具有第一导电类型的第一对MOS晶体管，其电耦合在该对感测位线之间。 该电耦合被提供为使得第一对MOS晶体管中的每一个具有电连接到该对感测位线中的相应一个和第一对MOS晶体管的第二源极/漏极端子的第一源极/漏极端子 电连接在一起。 第一导电类型的第一对MOS晶体管被配置为具有不同的阈值电压或支持不同的阈值电压偏置。 第二MOS读出放大器具有第一对第二导电类型的MOS晶体管，它们在一对感测位线之间电耦合。

公开(公告)号：US20110103166A1

公开(公告)日：2011-05-05

申请号：US12987539

申请日：2011-01-10

申请人： YOUNG-SUN MIN ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

发明人： YOUNG-SUN MIN ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

IPC分类号： G11C7/06 ,  H03F3/68 ,  H03F3/16 ,  G06F17/50

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C7/065 ,  G11C2207/002

摘要： A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

摘要翻译： 用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。 在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。

公开(公告)号：US07869239B2

公开(公告)日：2011-01-11

申请号：US12078724

申请日：2008-04-03

申请人： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

发明人： Young-Sun Min ,  Kyu-Chan Lee ,  Chul-Woo Yi ,  Jong-Hyun Choi

IPC分类号： G11C5/02

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C7/065 ,  G11C2207/002

摘要： A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

摘要翻译： 用于半导体存储器件的位线读出放大器的布局结构包括布置成由第一列选择线信号共享和电控制的第一和第二位线读出放大器，并且每个包括多个晶体管。 在该布局结构中，形成第一位线读出放大器的多个晶体管中的每一个被布置成不与形成第二位线读出放大器的任何晶体管共享有源区。

公开(公告)号：US07298655B2

公开(公告)日：2007-11-20

申请号：US11073765

申请日：2005-03-08

申请人： Jong-Hyun Choi ,  Young-Sun Min

发明人： Jong-Hyun Choi ,  Young-Sun Min

IPC分类号： G11C16/04

CPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C2207/005

摘要： A semiconductor memory includes a memory cell array, a sense amplifier, an isolation device interposed between the sense amplifier and a bit line of the memory cell array, and circuitry for transferring a charge contained in a memory cell of memory cell array to the bit line while the isolation device electrically isolates the bit line from the sense amplifier, and, after the charge is transferred to the bit line, for causing the isolation device to electrically connect the bit line to the sense amplifier.

摘要翻译： 半导体存储器包括存储单元阵列，读出放大器，插入在读出放大器和存储单元阵列的位线之间的隔离装置，以及用于将包含在存储单元阵列的存储单元中的电荷传送到位线 而隔离装置将位线与读出放大器电隔离，并且在电荷被传送到位线之后，用于使隔离装置将位线电连接到读出放大器。