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    METHOD AND CIRCUIT FOR DRIVING WORD LINE OF MEMORY CELL
    3.
    发明申请
    METHOD AND CIRCUIT FOR DRIVING WORD LINE OF MEMORY CELL 有权
    用于驱动存储单元字线的方法和电路

    公开(公告)号：US20080159055A1

    公开(公告)日：2008-07-03

    申请号：US11875171

    申请日：2007-10-19

    申请人： Yun-sang LEE ,  Jung-bae LEE

    发明人： Yun-sang LEE ,  Jung-bae LEE

    IPC分类号： G11C8/00

    CPC分类号： G11C8/08

    摘要： A method and circuit are provided for driving a word line. The word line driving circuit includes first and second power drivers, a switching unit and a word line driver. The first power driver is driven to a boosting voltage level and the second power driver is driven to an internal power voltage level. The switching unit transfers a first output of the first power driver to the word line driver in response to a first switching signal and transfers a second output of the second power driver to the word line driver in response to a second switching signal. The word line driver alternately drives a word line to the first output and the second output transferred from the switching unit in response to a word line driving signal.

    摘要翻译： 提供了用于驱动字线的方法和电路。 字线驱动电路包括第一和第二电源驱动器，开关单元和字线驱动器。 第一个功率驱动器被驱动到升压电压电平，第二个功率驱动器被驱动到内部电源电压电平。 切换单元响应于第一切换信号将第一功率驱动器的第一输出传送到字线驱动器，并响应于第二切换信号将第二功率驱动器的第二输出传送到字线驱动器。 字线驱动器响应于字线驱动信号交替地驱动字线到第一输出和从开关单元传送的第二输出。

    SYSTEM AND METHOD FOR SELECTIVELY PERFORMING SINGLE-ENDED AND DIFFERENTIAL SIGNALING
    5.
    发明申请
    SYSTEM AND METHOD FOR SELECTIVELY PERFORMING SINGLE-ENDED AND DIFFERENTIAL SIGNALING 有权
    选择性地进行单端和差分信号的系统和方法

    公开(公告)号：US20130163692A1

    公开(公告)日：2013-06-27

    申请号：US13775543

    申请日：2013-02-25

    申请人： Hoe-ju CHUNG ,  Jung-bae LEE

    发明人： Hoe-ju CHUNG ,  Jung-bae LEE

    IPC分类号： H04B1/02

    CPC分类号： H04L25/0264 ,  H04L25/0272

    摘要： In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

    摘要翻译： 在通信系统中，使用单端或差分信令有选择地发送数据。 相对于具有不同相对相位的多个时钟信号发送数据。 当使用单端信令发送数据时，相邻信号线上的数据相对于多个时钟信号在不同时刻进行逻辑转换。

    Multimode data buffer and method for controlling propagation delay time
    6.
    发明申请
    Multimode data buffer and method for controlling propagation delay time 有权
    多模数据缓冲器和传播延迟时间控制方法

    公开(公告)号：US20080106952A1

    公开(公告)日：2008-05-08

    申请号：US11979496

    申请日：2007-11-05

    申请人： Seong-young SEO ,  Jung-bae LEE ,  Byong-mo MOON

    发明人： Seong-young SEO ,  Jung-bae LEE ,  Byong-mo MOON

    IPC分类号： G11C7/10

    CPC分类号： G11C7/109 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1084

    摘要： A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

    摘要翻译： 诸如数据选通输入缓冲器或数据输入缓冲器的数据缓冲器，其可以以多种模式操作，例如单模（SM）和双模（DM），并且其中通过提供信号选择模式， 例如诸如地址信号或外部命令信号的外部信号。 一种可用于SM / DM两用的数据缓冲器，可以提高数据设置/保持余量。 一种包括上述数据缓冲器中的一个或多个的半导体存储器件。 一种用于控制传播延迟时间的方法，其可以改善SM / DM两用数据缓冲器中的数据建立/保持余量。

    MEMORY DEVICES WITH SELECTIVE ERROR CORRECTION CODE
    7.
    发明申请
    MEMORY DEVICES WITH SELECTIVE ERROR CORRECTION CODE 有权
    具有选择性错误修正代码的存储器件

    公开(公告)号：US20140013183A1

    公开(公告)日：2014-01-09

    申请号：US13915179

    申请日：2013-06-11

    申请人： Young-Soo SOHN ,  Chul-Woo PARK ,  Jong-Pil SON ,  Jung-bae LEE

    发明人： Young-Soo SOHN ,  Chul-Woo PARK ,  Jong-Pil SON ,  Jung-bae LEE

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1012 ,  G06F11/10 ,  G06F11/1024 ,  G06F11/1048 ,  G06F11/106 ,  G11C2029/0411 ,  H03M13/3707

    摘要： An error correction apparatus includes an error correction circuit configured to selectively perform error correction on a portion of data that is at least one of written to and read from a plurality of memory cells of a memory device. The portion of data is at least one of written to and read from a subset of the plurality of memory cells, and the subset includes only fail cells among the plurality of memory cells. The error correction apparatus further includes a fail address storage circuit configured to store address information for the fail cells.

    摘要翻译： 纠错装置包括：纠错电路，被配置为对存储器件的多个存储单元的至少一个写入和读出的数据的一部分进行选择性地执行纠错。 数据的部分是从多个存储器单元的子集写入和读出中的至少一个，并且该子集仅包括多个存储器单元中的故障单元。 误差校正装置还包括故障地址存储电路，其被配置为存储故障单元的地址信息。

    METHOD OF CONTROLLING INTERNAL VOLTAGE AND MULTI-CHIP PACKAGE MEMORY PREPARED USING THE SAME
    8.
    发明申请
    METHOD OF CONTROLLING INTERNAL VOLTAGE AND MULTI-CHIP PACKAGE MEMORY PREPARED USING THE SAME 有权
    控制内部电压的方法和使用其制备的多芯片封装内存

    公开(公告)号：US20090125687A1

    公开(公告)日：2009-05-14

    申请号：US12266716

    申请日：2008-11-07

    申请人： Moon-sook PARK ,  Hoe-ju CHUNG ,  Jung-bae LEE

    发明人： Moon-sook PARK ,  Hoe-ju CHUNG ,  Jung-bae LEE

    IPC分类号： G06F12/00

    CPC分类号： G11C5/147 ,  G11C5/04

    摘要： The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device.

    摘要翻译： 本发明一般涉及一种多芯片封装（MCP）存储器件，尤其涉及但不限于具有减小尺寸的MCP存储器件。 在一个实施例中，MCP存储器件包括：传送存储器芯片; 以及多个存储器芯片，其耦合到所述传送存储器芯片，所述多个存储器芯片中的每一个包括内部电压产生电路，所述传送存储器芯片被配置为从所述MCP存储器设备的外部接收多个命令信号，所述传送存储器芯片 还被配置为基于所述多个命令信号将多个控制信号输出到所述多个存储器芯片。 本发明的实施例还涉及一种控制MCP存储器件的内部电压的方法。

    MULTI-CHIP MEMORY DEVICE WITH STACKED MEMORY CHIPS, METHOD OF STACKING MEMORY CHIPS, AND METHOD OF CONTROLLING OPERATION OF MULTI-CHIP PACKAGE MEMORY
    9.
    发明申请
    MULTI-CHIP MEMORY DEVICE WITH STACKED MEMORY CHIPS, METHOD OF STACKING MEMORY CHIPS, AND METHOD OF CONTROLLING OPERATION OF MULTI-CHIP PACKAGE MEMORY 有权
    具有堆叠存储器芯片的多芯片存储器件，堆叠存储器芯片的方法和控制多芯片封装存储器操作的方法

    公开(公告)号：US20090091962A1

    公开(公告)日：2009-04-09

    申请号：US12238720

    申请日：2008-09-26

    申请人： Hoe-ju CHUNG ,  Jung-bae LEE ,  Uk-song KANG

    发明人： Hoe-ju CHUNG ,  Jung-bae LEE ,  Uk-song KANG

    IPC分类号： G11C5/02 ,  H01L21/00

    CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C5/04 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips.

    摘要翻译： 多芯片存储器件包括传送输入/输出信号的传输存储器芯片，每个包括具有指定存储体的存储器阵列的堆叠多个存储器芯片，以及通过存储芯片堆栈从传输存储器芯片向上延伸的信号路径 通信输入/输出信号，其中堆叠的多个存储器芯片中的每个存储器芯片的每个存储体通常被寻址以在读取操作期间提供读取数据，并且在写入操作期间接收写入数据，并且在堆叠的多个存储器内垂直对准 筹码

    STACKED MEMORY DEVICE
    10.
    发明申请
    STACKED MEMORY DEVICE 有权
    堆叠存储器件

    公开(公告)号：US20090039492A1

    公开(公告)日：2009-02-12

    申请号：US12123583

    申请日：2008-05-20

    申请人： Uk-song KANG ,  Jung-bae LEE ,  Hoe-ju CHUNG

    发明人： Uk-song KANG ,  Jung-bae LEE ,  Hoe-ju CHUNG

    IPC分类号： H01L23/02

    CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C5/063 ,  H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15331 ,  H01L2224/05599

    摘要： A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central portion having bond pads seating the corresponding memory device and a peripheral portion having a plurality of through silicon vias (TSVs). The respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips.

    摘要翻译： 半导体存储器件包括堆叠的多个插入器芯片，每个插入器芯片放置较小的对应的存储器芯片，其中堆叠的多个插入器芯片中的最下层插入器芯片安装在缓冲芯片上。 堆叠的多个插入器芯片中的每一个包括具有连接衬垫对应的存储器件的中心部分和具有多个穿通硅通孔（TSV）的外围部分。 堆叠的多个插入器芯片中的相邻插入器芯片的相应多个TSV通过垂直连接元件连接，以形成从相应存储器芯片向缓冲器芯片传送写入数据和从其读取数据的多个内部信号路径。