公开(公告)号：US08891324B2

公开(公告)日：2014-11-18

申请号：US13915338

申请日：2013-06-11

申请人： Chul-woo Yi ,  Seong-jin Jang ,  Jin-seok Kwak ,  Tai-young Ko ,  Joung-yeal Kim ,  Sang-yun Kim ,  Sang-kyun Park ,  Jung-bae Lee

发明人： Chul-woo Yi ,  Seong-jin Jang ,  Jin-seok Kwak ,  Tai-young Ko ,  Joung-yeal Kim ,  Sang-yun Kim ,  Sang-kyun Park ,  Jung-bae Lee

IPC分类号： G11C7/00 ,  G11C5/06 ,  G11C7/06 ,  H01L27/02 ,  H01L27/105 ,  G11C7/18 ,  G11C11/4091 ,  H01L27/108

CPC分类号： G11C5/063 ,  G11C7/062 ,  G11C7/065 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10897 ,  Y10T29/41

摘要： A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

摘要翻译： 一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和 第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管， 电容器块电连接到边缘检测放大块。

公开(公告)号：US08482951B2

公开(公告)日：2013-07-09

申请号：US13023738

申请日：2011-02-09

申请人： Chul-woo Yi ,  Seong-jin Jang ,  Jin-seok Kwak ,  Tai-young Ko ,  Joung-yeal Kim ,  Sang-yun Kim ,  Sang-kyun Park ,  Jung-bae Lee

发明人： Chul-woo Yi ,  Seong-jin Jang ,  Jin-seok Kwak ,  Tai-young Ko ,  Joung-yeal Kim ,  Sang-yun Kim ,  Sang-kyun Park ,  Jung-bae Lee

IPC分类号： G11C5/02

CPC分类号： G11C5/063 ,  G11C7/062 ,  G11C7/065 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10897 ,  Y10T29/41

摘要： A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

摘要翻译： 一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和 第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管， 电容器块电连接到边缘检测放大块。

公开(公告)号：US20130250645A1

公开(公告)日：2013-09-26

申请号：US13897515

申请日：2013-05-20

申请人： Sang-yun Kim ,  Tai-young Ko

发明人： Sang-yun Kim ,  Tai-young Ko

IPC分类号： G11C5/06

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C7/02 ,  G11C11/4097

摘要： A semiconductor memory device including: first and second memory cell arrays each including at least one word line, at least three bit lines, and memory cells; and a sense amplifier area disposed between the first and second memory cell arrays and including a sense amplifier circuit for sensing and amplifying data of the memory cells, wherein the at least three bit lines of the first memory cell array and the at least three bit lines of the second memory cell array extend in a first direction and the at least three bit lines of the first and the second memory cell arrays are respectively connected to data lines disposed in a second direction, and wherein a bit line located between two of the at least three bit lines of each of the first and the second memory cell arrays is connected to an outermost data line of the data lines.

摘要翻译： 一种半导体存储器件，包括：第一和第二存储单元阵列，每个包括至少一个字线，至少三个位线和存储单元; 以及设置在第一和第二存储单元阵列之间并包括用于感测和放大存储器单元的数据的读出放大器电路的读出放大器区域，其中第一存储单元阵列的至少三个位线和至少三个位线 的第二存储单元阵列在第一方向上延伸，并且第一和第二存储单元阵列的至少三个位线分别连接到沿第二方向布置的数据线，并且其中位于两个at 第一和第二存储单元阵列中的每一个的至少三条位线连接到数据线的最外层数据线。

公开(公告)号：US08467216B2

公开(公告)日：2013-06-18

申请号：US12917832

申请日：2010-11-02

申请人： Sang-yun Kim ,  Tai-young Ko

发明人： Sang-yun Kim ,  Tai-young Ko

IPC分类号： G11C5/06

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C7/02 ,  G11C11/4097

摘要： A semiconductor memory device including: first and second memory cell arrays each including at least one word line, at least three bit lines, and memory cells; and a sense amplifier area disposed between the first and second memory cell arrays and including a sense amplifier circuit for sensing and amplifying data of the memory cells, wherein the at least three bit lines of the first memory cell array and the at least three bit lines of the second memory cell array extend in a first direction and the at least three bit lines of the first and the second memory cell arrays are respectively connected to data lines disposed in a second direction, and wherein a bit line located between two of the at least three bit lines of each of the first and the second memory cell arrays is connected to an outermost data line of the data lines.

摘要翻译： 一种半导体存储器件，包括：第一和第二存储单元阵列，每个包括至少一个字线，至少三个位线和存储单元; 以及设置在第一和第二存储单元阵列之间并包括用于感测和放大存储器单元的数据的读出放大器电路的读出放大器区域，其中第一存储单元阵列的至少三个位线和至少三个位线 的第二存储单元阵列在第一方向上延伸，并且第一和第二存储单元阵列的至少三个位线分别连接到沿第二方向布置的数据线，并且其中位于两个at 第一和第二存储单元阵列中的每一个的至少三条位线连接到数据线的最外层数据线。

公开(公告)号：US20110182099A1

公开(公告)日：2011-07-28

申请号：US12917832

申请日：2010-11-02

申请人： Sang-yun Kim ,  Tai-young Ko

发明人： Sang-yun Kim ,  Tai-young Ko

IPC分类号： G11C5/02

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C7/02 ,  G11C11/4097

摘要： A semiconductor memory device including: first and second memory cell arrays each including at least one word line, at least three bit lines, and memory cells; and a sense amplifier area disposed between the first and second memory cell arrays and including a sense amplifier circuit for sensing and amplifying data of the memory cells, wherein the at least three bit lines of the first memory cell array and the at least three bit lines of the second memory cell array extend in a first direction and the at least three bit lines of the first and the second memory cell arrays are respectively connected to data lines disposed in a second direction, and wherein a bit line located between two of the at least three bit lines of each of the first and the second memory cell arrays is connected to an outermost data line of the data lines.

摘要翻译： 一种半导体存储器件，包括：第一和第二存储单元阵列，每个包括至少一个字线，至少三个位线和存储单元; 以及设置在第一和第二存储单元阵列之间并包括用于感测和放大存储器单元的数据的读出放大器电路的读出放大器区域，其中第一存储单元阵列的至少三个位线和至少三个位线 的第二存储单元阵列在第一方向上延伸，并且第一和第二存储单元阵列的至少三个位线分别连接到沿第二方向布置的数据线，并且其中位于两个at 第一和第二存储单元阵列中的每一个的至少三条位线连接到数据线的最外层数据线。

公开(公告)号：US07688651B2

公开(公告)日：2010-03-30

申请号：US11756750

申请日：2007-06-01

申请人： Chi-wook Kim ,  Tai-young Ko

发明人： Chi-wook Kim ,  Tai-young Ko

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/50012

摘要： A method of regulating timing of control signals in an integrated circuit memory device includes generating a pulse signal having a pulse width representing a time period between a rising edge of a first control signal and a rising edge of a second control signal that is activated after the first control signal. Based on the pulse width of the pulse signal, it is determined whether a timing margin between activation of the first control signal and activation of the second control signal is within a predetermined range, and the timing margin is adjusted responsive to the determination. For example, the pulse signal may be a timing measurement signal including a first pulse signal representing a first timing margin between a word line enable signal and a bit line sensing enable signal, a second pulse signal representing a second timing margin between a column select line enable signal and a first read pulse signal, and a third pulse signal representing a third timing margin between a word line disable signal and a bit line equalizing signal. Related devices are also discussed.

摘要翻译： 一种调节集成电路存储器件中的控制信号定时的方法包括：生成脉冲信号，该脉冲信号具有表示在第一控制信号的上升沿和第二控制信号的上升沿之间的时间周期的脉冲宽度， 第一控制信号。 基于脉冲信号的脉冲宽度，确定第一控制信号的激活和第二控制信号的激活之间的定时裕度是否在预定范围内，并且响应于该确定来调整定时裕度。 例如，脉冲信号可以是定时测量信号，其包括表示字线使能信号和位线检测使能信号之间的第一定时裕度的第一脉冲信号，表示列选择线之间的第二定时裕度的第二脉冲信号 使能信号和第一读取脉冲信号，以及表示字线禁止信号和位线均衡信号之间的第三定时裕度的第三脉冲信号。 还讨论了相关设备。

公开(公告)号：US20070280033A1

公开(公告)日：2007-12-06

申请号：US11756750

申请日：2007-06-01

申请人： Chi-wook Kim ,  Tai-young Ko

发明人： Chi-wook Kim ,  Tai-young Ko

IPC分类号： G11C29/00 ,  G11C7/00 ,  G11C8/00 ,  G11C7/02

CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/50012

摘要： A method of regulating timing of control signals in an integrated circuit memory device includes generating a pulse signal having a pulse width representing a time period between a rising edge of a first control signal and a rising edge of a second control signal that is activated after the first control signal. Based on the pulse width of the pulse signal, it is determined whether a timing margin between activation of the first control signal and activation of the second control signal is within a predetermined range, and the timing margin is adjusted responsive to the determination. For example, the pulse signal may be a timing measurement signal including a first pulse signal representing a first timing margin between a word line enable signal and a bit line sensing enable signal, a second pulse signal representing a second timing margin between a column select line enable signal and a first read pulse signal, and a third pulse signal representing a third timing margin between a word line disable signal and a bit line equalizing signal. Related devices are also discussed.

摘要翻译： 一种调节集成电路存储器件中的控制信号定时的方法包括：生成脉冲信号，该脉冲信号具有表示在第一控制信号的上升沿和第二控制信号的上升沿之间的时间周期的脉冲宽度， 第一控制信号。 基于脉冲信号的脉冲宽度，确定第一控制信号的激活和第二控制信号的激活之间的定时裕度是否在预定范围内，并且响应于该确定来调整定时裕度。 例如，脉冲信号可以是定时测量信号，其包括表示字线使能信号和位线检测使能信号之间的第一定时裕度的第一脉冲信号，表示列选择线之间的第二定时裕度的第二脉冲信号 使能信号和第一读取脉冲信号，以及表示字线禁止信号和位线均衡信号之间的第三定时裕度的第三脉冲信号。 还讨论了相关设备。