公开(公告)号：US07825478B2

公开(公告)日：2010-11-02

申请号：US12407823

申请日：2009-03-20

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： H01L29/00 ,  H01L21/425

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material.

摘要翻译： 描述了用于电阻读出存储器的极性依赖开关。 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻式感测存储单元电连接到位触点。 源极接触和位触点用掺杂剂材料非对称地注入。

公开(公告)号：US20100210095A1

公开(公告)日：2010-08-19

申请号：US12774018

申请日：2010-05-05

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： H01L21/425

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： Methods of forming polarity dependent switches for resistive sense memory are described. Methods for forming a memory unit include implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor, and electrically connecting a resistive sense memory cell to the bit contact. The resistive sense memory cell is configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.

摘要翻译： 描述了形成电阻式读出存储器的极性依赖开关的方法。 用于形成存储器单元的方法包括在源极接触中比半导体晶体管的位接触更多地注入掺杂剂材料，并且将电阻性感测存储器单元电连接到位触点。 电阻读出存储单元被配置为在电流通过电阻读出存储单元时在高电阻状态和低电阻状态之间切换。

公开(公告)号：US20100117160A1

公开(公告)日：2010-05-13

申请号：US12407823

申请日：2009-03-20

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： H01L29/00 ,  H01L21/425

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material.

摘要翻译： 描述了用于电阻读出存储器的极性依赖开关。 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻式感测存储单元电连接到位触点。 源极接触和位触点用掺杂剂材料非对称地注入。

公开(公告)号：US20120039111A1

公开(公告)日：2012-02-16

申请号：US13278334

申请日：2011-10-21

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： G11C11/00 ,  H01L29/78 ,  H01L45/00

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.

摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。

公开(公告)号：US08072014B2

公开(公告)日：2011-12-06

申请号：US12903301

申请日：2010-10-13

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： G11C11/00 ,  H01L29/78

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.

摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。

公开(公告)号：US07935619B2

公开(公告)日：2011-05-03

申请号：US12774018

申请日：2010-05-05

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： H01L21/425

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： Methods of forming polarity dependent switches for resistive sense memory are described. Methods for forming a memory unit include implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor, and electrically connecting a resistive sense memory cell to the bit contact. The resistive sense memory cell is configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.

摘要翻译： 描述了形成电阻式读出存储器的极性依赖开关的方法。 用于形成存储器单元的方法包括在源极接触中比半导体晶体管的位接触更多地注入掺杂剂材料，并且将电阻性感测存储器单元电连接到位触点。 电阻读出存储单元被配置为在电流通过电阻读出存储单元时在高电阻状态和低电阻状态之间切换。

公开(公告)号：US20110032748A1

公开(公告)日：2011-02-10

申请号：US12903301

申请日：2010-10-13

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： G11C11/00 ,  H01L29/78

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.

摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。

公开(公告)号：US08508980B2

公开(公告)日：2013-08-13

申请号：US13278334

申请日：2011-10-21

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： H01L29/78 ,  H01L45/00 ,  G11C11/00

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.

摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。

公开(公告)号：US20120074466A1

公开(公告)日：2012-03-29

申请号：US12891982

申请日：2010-09-28

申请人： Dadi Setiadi ,  Peter Nicholas Manos ,  Hsing-Kuen Liou ,  Paramasivan Kamatchi Subramanian ,  Young Pil Kim ,  Hyung-Kyu Lee ,  Maroun Georges Khoury ,  Chulmin Jung

发明人： Dadi Setiadi ,  Peter Nicholas Manos ,  Hsing-Kuen Liou ,  Paramasivan Kamatchi Subramanian ,  Young Pil Kim ,  Hyung-Kyu Lee ,  Maroun Georges Khoury ,  Chulmin Jung

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： H01L21/8239 ,  H01L21/823487 ,  H01L27/1052 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2481

摘要： A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell.

摘要翻译： 存储器阵列包括基本电路层和顺序堆叠以形成存储器阵列的多个存储器阵列层。 每个存储器阵列层电耦合到基极电路层。 每个存储器阵列层包括多个存储器单元。 每个存储单元包括电耦合到存储单元的垂直柱状晶体管。

公开(公告)号：US08617952B2

公开(公告)日：2013-12-31

申请号：US12891966

申请日：2010-09-28

申请人： Young Pil Kim ,  Hyung-Kew Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

发明人： Young Pil Kim ,  Hyung-Kew Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

IPC分类号： H01L21/336

CPC分类号： H01L45/1233 ,  H01L27/228 ,  H01L27/2454 ,  H01L45/1206

摘要： A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

摘要翻译： 一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。 每个柱结构形成具有与顶表面正交的顶表面和侧表面的垂直柱状晶体管。 然后将硬化物质注入垂直柱晶体管顶表面。 然后，垂直柱状晶体管侧面被氧化，形成侧面氧化层。 去除侧面氧化物层以形成具有圆形侧表面的垂直柱状晶体管。