公开(公告)号：US08203869B2

公开(公告)日：2012-06-19

申请号：US12326184

申请日：2008-12-02

申请人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

发明人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

IPC分类号： G11C11/00

CPC分类号： G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

摘要翻译： 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域在电磁变化存储单元和栅极之间电连接。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。

公开(公告)号：US08638597B2

公开(公告)日：2014-01-28

申请号：US13476368

申请日：2012-05-21

申请人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

发明人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

IPC分类号： G11C11/00

CPC分类号： G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

摘要翻译： 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域电连接在r磁阻变化存储器单元和栅极之间。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。

公开(公告)号：US20120230094A1

公开(公告)日：2012-09-13

申请号：US13476368

申请日：2012-05-21

申请人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

发明人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

IPC分类号： G11C11/16

CPC分类号： G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

摘要翻译： 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域电连接在r磁阻变化存储器单元和栅极之间。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。

公开(公告)号：US20100135066A1

公开(公告)日：2010-06-03

申请号：US12326184

申请日：2008-12-02

申请人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

发明人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

IPC分类号： G11C7/00 ,  G11C11/16

CPC分类号： G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

摘要翻译： 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域在电磁变化存储单元和栅极之间电连接。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。

公开(公告)号：US07825478B2

公开(公告)日：2010-11-02

申请号：US12407823

申请日：2009-03-20

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： H01L29/00 ,  H01L21/425

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material.

摘要翻译： 描述了用于电阻读出存储器的极性依赖开关。 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻式感测存储单元电连接到位触点。 源极接触和位触点用掺杂剂材料非对称地注入。

公开(公告)号：US20100210095A1

公开(公告)日：2010-08-19

申请号：US12774018

申请日：2010-05-05

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： H01L21/425

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： Methods of forming polarity dependent switches for resistive sense memory are described. Methods for forming a memory unit include implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor, and electrically connecting a resistive sense memory cell to the bit contact. The resistive sense memory cell is configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.

摘要翻译： 描述了形成电阻式读出存储器的极性依赖开关的方法。 用于形成存储器单元的方法包括在源极接触中比半导体晶体管的位接触更多地注入掺杂剂材料，并且将电阻性感测存储器单元电连接到位触点。 电阻读出存储单元被配置为在电流通过电阻读出存储单元时在高电阻状态和低电阻状态之间切换。

公开(公告)号：US20100117160A1

公开(公告)日：2010-05-13

申请号：US12407823

申请日：2009-03-20

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： H01L29/00 ,  H01L21/425

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material.

摘要翻译： 描述了用于电阻读出存储器的极性依赖开关。 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻式感测存储单元电连接到位触点。 源极接触和位触点用掺杂剂材料非对称地注入。

公开(公告)号：US20120039111A1

公开(公告)日：2012-02-16

申请号：US13278334

申请日：2011-10-21

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： G11C11/00 ,  H01L29/78 ,  H01L45/00

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.

摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。

公开(公告)号：US08072014B2

公开(公告)日：2011-12-06

申请号：US12903301

申请日：2010-10-13

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： G11C11/00 ,  H01L29/78

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.

摘要翻译： 存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。 半导体晶体管包括形成在基板上的栅极元件。 半导体晶体管包括源极触点和位触点。 门元件电连接源触点和触点触点。 电阻读出存储单元电连接到位触点。 源触点被更多地注入掺杂剂材料，然后进行位接触。

公开(公告)号：US07935619B2

公开(公告)日：2011-05-03

申请号：US12774018

申请日：2010-05-05

申请人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

发明人： Chulmin Jung ,  Maroun Georges Khoury ,  Yong Lu ,  Young Pil Kim

IPC分类号： H01L21/425

CPC分类号： G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L29/1083

摘要： Methods of forming polarity dependent switches for resistive sense memory are described. Methods for forming a memory unit include implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor, and electrically connecting a resistive sense memory cell to the bit contact. The resistive sense memory cell is configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.

摘要翻译： 描述了形成电阻式读出存储器的极性依赖开关的方法。 用于形成存储器单元的方法包括在源极接触中比半导体晶体管的位接触更多地注入掺杂剂材料，并且将电阻性感测存储器单元电连接到位触点。 电阻读出存储单元被配置为在电流通过电阻读出存储单元时在高电阻状态和低电阻状态之间切换。